PSD931F1-15UI View Datasheet(PDF) - STMicroelectronics
Part Name
Description
Manufacturer
PSD931F1-15UI Datasheet PDF : 94 Pages
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Preliminary Information
The
PSD9XX
Functional
Blocks
(cont.)
Table 21. Port Operating Mode Settings
Mode
Defined In
PSDsoft
MCU I/O
Declare pins only
PLD I/O
Data Port
(Port A)
Address Out
(Port A,B)
Address In
(Port A,B,C,D)
JTAG ISP
*NA = Not Applicable
Logic or chip
select equations
Selected for MCU
with non-mux bus
Declare pins only
Declare pins only
Declare pins only
Control
Register
Setting
at Run-Time
0
NA
NA
1
NA
NA
PSD9XX Family
Direction
Register
Setting
at Run-Time
1 = output,
0 = input,
NA
1
NA
NA
9.4.2.1 MCU I/O Mode
In the MCU I/O Mode, the microcontroller uses the PSD9XX ports to expand its own
I/O ports. By setting up the CSIOP space, the ports on the PSD9XX are mapped into the
microcontroller address space. The addresses of the ports are listed in Table 7.
A port pin can be put into MCU I/O mode by writing a ‘0’ to the corresponding bit in the
Control Register. The MCU I/O direction may be changed by writing to the corresponding
bit in the Direction Register. See the subsection on the Direction Register in the “Port
Registers” section. When the pin is configured as an output, the content of the Data Out
Register drives the pin. When configured as an input, the microcontroller can read the port
input through the Data In buffer. See Figure 19.
Ports C and D do not have Control Registers, and are in MCU I/O mode by default. They
can be used for PLD I/O if they are specified in PSDsoft.
9.4.2.2 PLD I/O Mode
The PLD I/O Mode uses a port as an input to the PLDs, and/or as an output from the
GPLD. The corresponding bit in the Direction Register must not be set to ‘1’ if the pin is
defined as a PLD input pin in PSDsoft. The PLD I/O Mode is specified in PSDsoft by
declaring the port pins, and then specifying an equation in PSDsoft.
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