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PSD8343V12UT View Datasheet(PDF) - STMicroelectronics

Part Name
Description
Manufacturer
PSD8343V12UT Datasheet PDF : 110 Pages
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PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2
External Chip Select
The CPLD also provides three External Chip Se-
lect (ECS0-ECS2) outputs on Port D pins that can
be used to select external devices. Each External
Chip Select (ECS0-ECS2) consists of one product
term that can be configured active High or Low.
The output enable of the pin is controlled by either
the output enable product term or the Direction
Register. (See Figure 31.)
Figure 31. Port D External Chip Select Signals
ENABLE (.OE)
DIRECTION
REGISTER
PT0
POLARITY
BIT
ENABLE (.OE)
PT1
POLARITY
BIT
ENABLE (.OE)
PT2
POLARITY
BIT
ECS0
PD0 PIN
DIRECTION
REGISTER
ECS1
PD1 PIN
DIRECTION
REGISTER
ECS2
PD2 PIN
AI02890
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