PSD8145V70UT View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

PSD8145V70UT

Flash In-System Programmable (ISP) Peripherals for 8-bit MCUs, 5V

STMicroelectronics 

PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2

Figure 40. Input to Output Disable / Enable

INPUT

tER

tEA

INPUT TO

OUTPUT

ENABLE/DISABLE

AI02863

Table 47. CPLD Combinatorial Timing (5V devices)

Symbol

Parameter

Conditions

-70

Min Max

-90

Min Max

-15

Min Max

Fast

PT

Aloc

Turbo

Off

Slew

rate1

Unit

CPLD Input Pin/

tPD

Feedback to CPLD

Combinatorial Output

20

25

32 + 2 + 10 – 2 ns

tEA

CPLD Input to CPLD

Output Enable

21

26

32

+ 10 – 2 ns

tER

CPLD Input to CPLD

Output Disable

21

26

32

+ 10 – 2 ns

tARP

CPLD Register Clear

or Preset Delay

21

26

33

+ 10 – 2 ns

tARPW

CPLD Register Clear

or Preset Pulse Width

10

20

29

+ 10

ns

tARD

CPLD Array Delay

Any

macrocell

11

16

22 + 2

ns

Note: 1. Fast Slew Rate output available on PA3-PA0, PB3-PB0, and PD2-PD0. Decrement times by given amount.

Table 48. CPLD Combinatorial Timing (3V devices)

Symbol

Parameter

Conditions

-12

Min Max

-15

Min Max

-20

Min Max

PT

Aloc

Turbo

Off

Slew

rate1

Unit

CPLD Input Pin/

tPD

Feedback to CPLD

Combinatorial Output

40

45

50 + 4 + 20 – 6 ns

tEA

CPLD Input to CPLD

Output Enable

43

45

50

+ 20 – 6 ns

tER

CPLD Input to CPLD

Output Disable

43

45

50

+ 20 – 6 ns

tARP

CPLD Register Clear

or

Preset Delay

40

43

48

+ 20 – 6 ns

tARPW

CPLD Register Clear

or

Preset Pulse Width

25

30

35

+ 20

ns

tARD

CPLD Array Delay

Any

macrocell

25

29

33 + 4

ns

Note: 1. Fast Slew Rate output available on PA3-PA0, PB3-PB0, and PD2-PD0. Decrement times by given amount.

80/110

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