PSD8345V20UT View Datasheet(PDF) - STMicroelectronics
Part Name
Description
Manufacturer
PSD8345V20UT Datasheet PDF : 110 Pages
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PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2
Table 55. READ Timing (5V devices)
Symbol
Parameter
Conditions
-70
Min Max
-90
Min Max
-15
Turbo
Min Max Off
Unit
tLVLX
ALE or AS Pulse Width
15
20
28
ns
tAVLX
Address Setup Time
(Note 3)
4
6
10
ns
tLXAX
Address Hold Time
(Note 3)
7
8
11
ns
tAVQV
Address Valid to Data Valid
(Note 3)
70
90
150 + 10 ns
tSLQV
CS Valid to Data Valid
75
100
150
ns
tRLQV
RD to Data Valid 8-Bit Bus
RD or PSEN to Data Valid
8-Bit Bus, 8031, 80251
(Note 5)
24
32
40
ns
(Note 2)
31
38
45
ns
tRHQX RD Data Hold Time
(Note 1)
0
0
0
ns
tRLRH
RD Pulse Width
(Note 1)
27
32
38
ns
tRHQZ RD to Data High-Z
(Note 1)
20
25
30
ns
tEHEL
E Pulse Width
27
32
38
ns
tTHEH R/W Setup Time to Enable
6
10
18
ns
tELTL
R/W Hold Time After Enable
0
0
0
ns
tAVPV
Address Input Valid to
Address Output Delay
(Note 4)
20
25
30
ns
Note: 1. RD timing has the same timing as DS, LDS, UDS, and PSEN signals.
2. RD and PSEN have the same timing.
3. Any input used to select an internal PSD function.
4. In multiplexed mode, latched addresses generated from ADIO delay to address output on any Port.
5. RD timing has the same timing as DS, LDS, and UDS signals.
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