PSD854512JIT View Datasheet(PDF) - STMicroelectronics
Part Name
Description
Manufacturer
PSD854512JIT Datasheet PDF : 110 Pages
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PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2
Table 62. Port A Peripheral Data Mode READ Timing (3V devices)
Symbol
Parameter
Conditions
-12
Min Max
-15
Min Max
-20
Turbo
Min Max Off
Unit
tAVQV–PA
Address Valid to Data Valid
(Note 3)
50
50
50 + 20 ns
tSLQV–PA
CSI Valid to Data Valid
37
45
50 + 20 ns
tRLQV–PA
RD to Data Valid
(Notes 1,4)
37
40
45
ns
RD to Data Valid 8031 Mode
45
45
50
ns
tDVQV–PA
Data In to Data Out Valid
38
40
45
ns
tQXRH–PA
RD Data Hold Time
0
0
0
ns
tRLRH–PA
RD Pulse Width
(Note 1)
36
36
46
ns
tRHQZ–PA
RD to Data High-Z
(Note 1)
36
40
45
ns
Figure 48. Peripheral I/O WRITE Timing
ALE /AS
A/D BUS
ADDRESS
DATA OUT
tWLQV (PA)
tWHQZ (PA)
WR
tDVQV (PA)
PORT A
DATA OUT
AI02898
Table 63. Port A Peripheral Data Mode WRITE Timing (5V devices)
Symbol
Parameter
Conditions
-70
-90
-15
Unit
Min Max Min Max Min Max
tWLQV–PA
WR to Data Propagation Delay
(Note 2)
25
35
40 ns
tDVQV–PA
Data to Port A Data Propagation Delay
(Note 5)
22
30
38 ns
tWHQZ–PA WR Invalid to Port A Tri-state
(Note 2)
20
25
33 ns
Note: 1. RD has the same timing as DS, LDS, UDS, and PSEN (in 8031 combined mode).
2. WR has the same timing as the E, LDS, UDS, WRL, and WRH signals.
3. Any input used to select Port A Data Peripheral mode.
4. Data is already stable on Port A.
5. Data stable on ADIO pins to data on Port A.
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