PSD935G1-C-90MI View Datasheet(PDF) - STMicroelectronics
Part Name
Description
Manufacturer
PSD935G1-C-90MI Datasheet PDF : 91 Pages
| |||
PSD9XX Family
The
PSD935G2
Functional
Blocks
(cont.)
PSD935G2
9.4.8 Port F – Functionality and Structure
Port F can be configured to perform one or more of the following functions:
t MCU I/O Mode
t PLD Input – as direct input ot the PLD array.
t Address In – additional high address inputs. Direct input to the PLD array.
t Latched Address Out – Provide latched address out per Table 18.
t Slew Rate – pins can be set up for fast slew rate.
t Data Port – connected to D[7:0] when Port F is configured as Data Port for a
non-multiplexed bus.
9.4.9 Port G – Functionality and Structure
Port G can be configured to perform one or more of the following functions:
t MCU I/O Mode
t Latched Address Out – Provide latched address out per Table 18.
t Open Drain – pins can be configured in Open Drain Mode
Figure 23. Ports E, F and G Structure
WR
ADDRESS
ALE
DATA OUT
REG.
DQ
DQ
G
DATA OUT
ADDRESS
A[ 7:0] OR A[15:8]
OUTPUT
MUX
PORT PIN
READ MUX
P
D
B
DATA IN
OUTPUT
SELECT
CONTROL REG.
DQ
WR
DIR REG.
DQ
WR
PLD INPUT (PORT F)
ISP OR BATTERY BACK-UP (PORT E)
CONFIGURATION
BIT
54
Share Link: 