STG3005A2STR View Datasheet(PDF) - STMicroelectronics
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Description
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STG3005A2STR Datasheet PDF : 85 Pages
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128-BIT 3D MULTIMEDIA ACCELERATOR
RIVA128ZX
6.4 LAYOUT OF FRAMEBUFFER CLOCK SIGNALS
Separate clock signals FBCLK0 and FBCLK1 are provided for each bank of memory to give reduced
clock skew and loading. Additionally there is a clock feedback loop between FBCLK2 and FBCLKFB.
It is recommended that long traces are used without tunable components. If the layout includes provision
for expansion to 8MBytes, the clock path to the 4MByte parts should be at the end of the trace, and the
clock path to the 8MByte expansion located between the RIVA128ZX and the 4MByte parts as shown in
Figure 32. FBCLK2 and FBCLKFB should be shorted together as close to the package as possible.
Figure 32. Recommended memory clock layout
FBCLK2
FBCLKFB
RIVA128ZX
FBCLK0
FBCLK1
Expansion
to 8MBytes
Bank 1
512K
x32
t
t
512K
x32
Bank 0
512K
x32
512K
x32
6.5 FRAMEBUFFER INTERFACE TIMING SPECIFICATION
Figure 33. SDRAM/SGRAM I/O timing diagram
FBCLKx
FBA[10:0], FBD[63:0]
FBD[63:0]
tCK
tCH
tCL
tAS, tDS
tAH, tDH
tAC
tLZ
tOH
Table 10. SDRAM/SGRAM I/O timing parameters
Symbol
Parameter
tCK
CLK period
tCH
CLK high time
tCL
CLK low time
tAS
Address setup time
tAH
Address hold time
tDS
Write data setup time
Min.
-10
-12
10
12
3.5
4.5
3.5
4.5
3
4
1
1
3
4
Max.
Unit
-10
-12
-
-
ns
-
-
ns
-
-
ns
-
ns
-
ns
-
ns
Notes
37/85
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