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SL20T0081 View Datasheet(PDF) - System Logic Semiconductor

Part Name
Description
Manufacturer
SL20T0081
System-Logic
System Logic Semiconductor 
SL20T0081 Datasheet PDF : 56 Pages
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SLS System Logic Semiconductor
SL20T0081
FUNCTION DESCRIPTION
MICROPROCESSOR INTERFACE
Chip Select Input
There are CE1 and CE2 pins for chip selection. The SL20T0081 can interface with an MPU only when CE1 is “L” and
CE2 is “H”. When these pins are set to any other combination, RS, RDB(E) and_WRB(RW) inputs are disabled and
D0to D7 are to be high impedance. And, in case of serial interface, the internal shift register and the counter are reset.
Parallel / Serial Interface
SL20T0081 has three types of interface with an MPU, which are one serial and two parallel interfaces. This parallel or
serial inter face is determined by PS pin.
Table 3. Parallel / Serial Interface Mode
PS
Type
CE1
H
Parallel
CE1
L
Serial
CE1
CE2
P68/80
Interface mode
H
CE2
L
6800-series MPU mode
8080-series MPU mode
CE2
*x
Serial-mode
*x :Don’t care
Parallel Interface (PS = “H”)
The 8-bit bi-directional data bus is used in parallel interface and the type of MPU is selected by P68/80 as shown
in table 4. The type of data transfer is determined by signals at RS, RD(E) and WR(R/W) as shown in table 5.
Table 4. Microprocessor Selection for Parallel Interface
P68/80
CE1
CE2
RS
RD(E)
H
CE1
CE2
RS
E
L
CE1
CE2
RS
RD
WR(R/W)
R/W
WR
D0 to D7
D0 to D7
D0 to D7
MPU bus
6800-series
8080-series
Table 5. Parallel Data Transfer
Common
6800-series
RS
RD
WR
(E)
(R/W)
H
H
H
H
H
L
L
H
H
L
H
L
8080-series
RD
WR
L
H
H
L
L
H
H
L
Description
Display data read out
Display data write
Register status read
Writes to internal register (instruction)

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