SLS System Logic Semiconductor
Figure 25. Reset Input Timing
RESET
Internal reset
operation
tRESETB
SL20T0081
tIRST
Table 26. Reset Input Timing
Item
Signal
RESET low pulse width
RESET
Reset time
-
Symbol
tRESETB
tIRST
Min.
30.0
-
(VDD = 2.4 to 3.6V, ta =-40 to +85oC)
Typ.
Max.
Unit
Remark
-
-
ns
-
60.0
ns
Figure 26. Display Control Output Timing
tDFR
CL
FR
Table 27. Display Control Output Timing
Item
Signal
Symbol
FR delay time
FR
tDFR
Min.
-
(VDD = 2.4 to 3.6V, ta =-40 to +85oC)
Typ.
Max.
Unit
Remark
20
80
ns
CL=50pF