C164CI/SI
C164CL/SL
Table 7
C164CI Registers, Ordered by Name (cont’d)
Name
Physical 8-Bit Description
Address Addr.
OPDAT
EDC4H X ---
P0H
b FF02H
81H
P0L
b FF00H
80H
P1H
b FF06H
83H
P1L
b FF04H
82H
P3
b FFC4H
E2H
P4
b FFC8H
E4H
P5
b FFA2H
D1H
P5DIDIS b FFA4H
D2H
P8
b FFD4H
EAH
PECC0
FEC0H
60H
PECC1
FEC2H
61H
PECC2
FEC4H
62H
PECC3
FEC6H
63H
PECC4
FEC8H
64H
PECC5
FECAH 65H
PECC6
FECCH 66H
PECC7
FECEH 67H
PICON
b F1C4H E E2H
POCON0H F082H E 41H
POCON0L F080H E 40H
POCON1H F086H E 43H
POCON1L F084H E 42H
POCON20 F0AAH E 55H
POCON3
F08AH E 45H
POCON4
F08CH E 46H
POCON8
F092H E 49H
PSW
b FF10H
88H
RP0H
b F108H E 84H
RSTCON b F1E0H m ---
OTP Progr. Interface Data Register
Port 0 High Reg. (Upper half of PORT0)
Port 0 Low Reg. (Lower half of PORT0)
Port 1 High Reg. (Upper half of PORT1)
Port 1 Low Reg. (Lower half of PORT1)
Port 3 Register
Port 4 Register (7 bits)
Port 5 Register (read only)
Port 5 Digital Input Disable Register
Port 8 Register (8 bits)
PEC Channel 0 Control Register
PEC Channel 1 Control Register
PEC Channel 2 Control Register
PEC Channel 3 Control Register
PEC Channel 4 Control Register
PEC Channel 5 Control Register
PEC Channel 6 Control Register
PEC Channel 7 Control Register
Port Input Threshold Control Register
Port P0H Output Control Register
Port P0L Output Control Register
Port P1H Output Control Register
Port P1L Output Control Register
Dedicated Pin Output Control Register
Port P3 Output Control Register
Port P4 Output Control Register
Port P8 Output Control Register
CPU Program Status Word
System Startup Config. Reg. (Rd. only)
Reset Control Register
Reset
Value
0000H
00H
00H
00H
00H
0000H
00H
XXXXH
0000H
00H
0000H
0000H
0000H
0000H
0000H
0000H
0000H
0000H
0000H
0011H
0011H
0011H
0011H
0000H
2222H
0010H
0022H
0000H
XXH
00XXH
Data Sheet
37
V2.0, 2001-05