ATSAM4LS4BA-AU View Datasheet(PDF) - Atmel Corporation

Part Name

Description

Manufacturer

ATSAM4LS4BA-AU

ATSAM ARM-based Flash MCU

Atmel Corporation 

ATSAM4L8/L4/L2

The internal regulator is connected to the VDDIN pin and its output VDDOUT feeds VDDCORE

in linear mode or through an inductor in switching mode. Figure 6-4 shows the power schematics

to be used. All I/O lines will be powered by the same power (VVDDIN=VVDDIO=VVDDANA).

Figure 6-4. Single Supply Mode

Main Supply

(1.68V-3.6V)

VLCDIN

VDDIO

VDDANA

BUCK/LDOn

(PA02)

VDDIN

VDDOUT

VDDCORE

LCD VPUMP

RC80M, OSC,

ADC, DAC, AC0/1,

RC32K, OSC32K,

BOD18, BOD33

REGULATOR

Core domain: CPU,

Peripherals, RAM, Flash,

RCSYS, PLL, DFLL,

RCFAST

Backup domain:

AST, WDT, EIC,

BPM, BSCIF

6.2.3 LCD Power Modes

6.2.3.1

Principle

LCD lines is powered using the device internal voltage sources provided by the LCDPWR block.

When enabled, the LCDPWR blocks will generate the VLCD, BIASL, BIASH voltages.

LCD pads are splitted into three clusters that can be powered independently namely clusters A,

B and C. A cluster can either be in GPIO mode or in LCD mode.

When a cluster is in GPIO mode, its VDDIO pin must be powered externally. None of its GPIO

pin can be used as a LCD line

When a cluster is in LCD mode, each clusters VDDIO pin can be either forced externally (1.8-

3.6V) or unconnected (nc). GPIOs in a cluster are not available when it is in LCD mode. A clus-

ter is set in LCD mode by the LCDCA controller when it is enabled depending on the number of

segments configured. The LCDPWR block is powered by the VLCDIN pin inside cluster A

When LCD feature is not used, VLCDIN must be always powered (1.8-3.6V). VLCD, CAPH,

CAPL, BIASH, BIASL can be left unconnected in this case

50

42023GS–SAM–03/2014

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