SD1010 View Datasheet(PDF) - Unspecified

Part Name

Description

Manufacturer

SD1010

Dual-Interface XGA TFT LCD Display Controller

Unspecified 

SmartASIC, Inc.

SD1010

3.4.2.

LCD interface

The SD1010 support both 24- and 48-bit RGB interfaces with XGA LCD panels from

various panel manufacturers. The LCD panel resolution and timing information is

stored in the external EEPROM. The information in the EEPROM includes timing

related to the output back porch, synchronization pulse width and valid data window.

The timing information is used to generate the frequency divider for the output PLL,

to lock the PLL output clock with HSYNC for the LCD data clock, and to

synchronize the output VSYNC and input VSYNC.

3.5. EEPROM interface

As mentioned in previous sections, the external EEPROM stores crucial information

for the SD1010 internal operations. The SD1010 interfaces with the EEPROM

through a 2-wire serial interface. The suggested EEPROM device is an industry

standard serial-interface EEPROM (24x08). The 2-wire serial interface scheme is

briefly described here and a detailed description can be found in public literature.

3.5.1.

2-wire serial interface

The 2-wire serial interface uses 2 wires, SCL and SDA. The SCL is driven by the

SD1010 and used mainly as the sampling clock. The SDA is a bi-directional signal

and used mainly as a data signal. Figure 4 shows the basic bit definitions of the 2-wire

serial interface.

The 2-wire serial interface supports random and sequential read operations. Figures 5

and 6 show the data sequences for random read and sequential read operations.

November, 1999

SmartASIC Confidential

19

Revision B

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