Si3000
FSYNC
Prim ary
Sec ondar y
Prim ary
SDI
D 15 – D 1 D 0 = 0 (Softw are FC Bit)
XM T D ata
Sec ondar y
U pdate
XM T D ata
SDO
R C V D ata
Sec ondar y
U pdate
R C V D ata
16 SCLKs
128 SCLKs
256 SCLKs
Figure 15. Secondary Request
FSYNC
(mode 0)
FSYNC
(mode 1)
SDI
D 15 D 14 D 13 D 12 D 11 D 10 D 9 D 8
0 0 0 A AA A A
D7 D6 D5 D4 D3 D2 D1 D0
DDDDDDDD
SDO
R/W
Figure 16. Secondary Communication Data Format—Write Cycle
FSYNC
(mode 0)
FSYNC
(mode 1)
SDI
SDO
D 15 D 14 D 13 D 12 D 11 D 10 D 9 D 8 D 7
D0
0 0 1 A AA A A
High Z
R/W
D7 D6 D5 D4 D3 D2 D1 D0
D D D D D D D D High Z
Figure 17. Secondary Frame Format—Read Cycle
16
Rev. 1.4