SI3000-C-GS View Datasheet(PDF) - Silicon Laboratories

Part Name

Description

Manufacturer

SI3000-C-GS

VOICEBAND CODEC WITH MICROPHONE/SPEAKER DRIVE

Silicon Laboratories 

4. Pin Descriptions: Si3000

Si3000

SPKRR 1

MBIA S 2

HDST 3

SDI 4

SDO 5

FSY NC 6

MCLK 7

SCLK 8

16 SPKRL

15 LINEO

14 GND

13 V A

12 V D

11 LINEI

10 MIC

9 RESET

Pin #

1

2

3

4

5

6

7

8

9

10

11

12

Pin Name

SPKRR

MBIAS

HDST

SDI

SDO

FSYNC

MCLK

SCLK

RESET

MIC

LINEI

VD

Description

Speaker Right Output.

Analog output capable of driving a 60  load.

Microphone bias output.

Handset Input/Output.

Handset analog input/output.

Serial Port Data In.

Serial communication and control data that is generated by the System DSP to the

Si3000.

Serial Port Data Out.

Serial communication data that is provided by the Si3000 to the system DSP.

Frame Sync Output.

Data framing signal that is used to indicate the start and stop of a communication data

frame.

Master Clock Input.

High speed master clock input. Generally supplied by the system crystal clock or DSP.

Serial Port Bit Clock Input/Output.

Controls the serial data on SDO and latches the data on SDI. This pin is an input in

slave mode and an output in master mode.

Reset.

An active low input that is used to reset all control registers to a defined initialized

state. Also used to bring the Si3000 out of sleep mode.

MIC Input.

Microphone level or line level input. This input contains selectable gain of 0, 10, 20, or

30 dB with a full scale input level of 1 VRMS.

Line Input.

Line level input with selectable gain of 0, 10, or 20 dB. The full scale input level is

1 VRMS.

Digital Supply Voltage.

Provides the digital supply voltage to the Si3000. Nominally either 5 or 3.3 V and

within 0.6 V of VA.

Rev. 1.4

27

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