CS8405A-CZ View Datasheet(PDF) - Cirrus Logic
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Description
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CS8405A-CZ Datasheet PDF : 37 Pages
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CS8405A
12. APPLICATIONS
12.1 Reset, Power Down and Start-up
When RST is low, the CS8405A enters a low pow-
er mode and all internal states are reset, including
the control port and registers, and the outputs are
disabled. When RST is high, the control port be-
comes operational and the desired settings should
be loaded into the control registers. Writing a 1 to
the RUN bit will then cause the part to leave the low
power state and begin operation.
12.2 ID Code and Revision Code
The CS8405A has a register that contains a four-
bit code to indicate that the addressed device is a
CS8405A. This is useful when other CS84XX fam-
ily members are resident in the same or similar
systems, allowing common software modules.
The CS8405A four-bit revision level code is also
available. This allows the software driver for the
CS8405A to identify which revision of the device is
in a particular system, and modify its behavior ac-
cordingly. To allow for future revisions, it is strongly
recommended that the revision code is read into a
variable area within the microcontroller, and used
wherever appropriate as revision details become
known.
12.3 Power Supply, Grounding, and PCB
layout
For most applications, the CS8405 can be operat-
ed from a single +5.0 V supply, following normal
supply decoupling practices, see Figure 5. “Rec-
ommended Connection Diagram for Software
Mode” on page 10. Note that the I²C protocol is
supported only in VL+ = 5.0 V mode. The VL+ sup-
plies should be decoupled with a 0.1 µF capacitor
to DGND to minimize AES3 transmitter induced
transients.
Extensive use of power and ground planes, ground
plane fill in unused areas and surface mount de-
coupling capacitors are recommended. Decou-
pling capacitors should be mounted on the same
side of the board as the CS8405A to minimize in-
ductance effects, and all decoupling capacitors
should be as close to the CS8405A as possible.
12.4 Synchronization of Multiple
CS8405As
The AES3 transmitters of multiple CS8405As can
be synchronized if all devices share the same mas-
ter clock, TCBL, and RST signals and all exit the
reset state on the same master clock falling edge.
The TCBL pin is used to synchronize multiple
CS8405A AES3 transmitters at the channel status
block boundaries. One CS8405A must have its
TCBL set to master; the others must be set to slave
TCBL. Alternatively, TCBL can be derived from ex-
ternal logic, whereby all CS8405A devices should
be set to slave TCBL.
DS469F2
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