SI3233-X-FM View Datasheet(PDF) - Silicon Laboratories

Part Name

Description

Manufacturer

SI3233-X-FM

PROSLIC® PROGRAMMABLE CMOS SLIC WITH RINGING/BATTERY VOLTAGE GENERATION

Silicon Laboratories 

Si3233

2.6. Two-Wire Impedance Matching

PCLK frequency and it can be approximately predicted

by the following equation:

The ProSLIC provides on-chip programmable two-wire

impedance settings to meet a wide variety of worldwide

two-wire return loss requirements. The two-wire

impedance is programmed by loading one of the eight

available impedance values into the TISS[2:0] bits of the

Two-Wire Impedance Synthesis Control register (direct

Register 10). If direct Register 10 is not explicitly set,

the default setting of 600 Ω will be loaded into the TISS

register.

The ProSLIC also provides a means to compensate for

degraded subscriber loop conditions involving

excessive line capacitance (leakage). The CLC[1:0] bits

of direct Register 10 increase the ac signal magnitude

to compensate for the additional loss at the high end of

the audio frequency range. The default setting of

CLC[2:0] assumes no line capacitance.

To support 600 Ω + 1 µF and 900 Ω + 2.16 µF

applications, an external resistor, RZREF, must be

inserted into the application circuit as shown in

Figure 15.

to TIP

C3

R8

STIPAC

RZREF

Si3233

TSETTLE

=

------6---4-------

FPCLK

2.8. PLL Free-run Operation

The Si3233 is capable of operating in the absence of a

valid PCLK signal. This feature can be enabled at any

time after initialization by setting the PFR bit (register

14, bit 3). When enabled, the Si3233 internally gates off

the buffered PCLK signal and applies a reference

voltage input to the PLL. This allows the DC/DC

converter to operate correctly and enables a nominal

battery voltage to remain on the line. The PCLK pin

must be held either high or low during PLL Free-run

operation. To exit the PLL Free-run mode, valid PCLK

and FSYNC signals must be reestablished and the

Si3233 RESET pin must be asserted. The direct and

indirect registers must then be reloaded with the desired

initialization settings. Capturing and storing the

calibration results (direct registers 98–107) before

entering the PLL free-run mode is recommended since

the results can then be manually reloaded after exiting

the PLL free-run mode without executing a calibration

routine. Note that audio signal generation will not be

accurate during this mode of operation and therefore it

is not recommended.

2.9. Interrupt Logic

SRINGAC

to RING

C4

R9

For 600 + 1 µF, RZREF = 12 kΩ and C3, C4 = 100 nF.

For 900 + 2.16 µF, RZREF = 18 kΩ and C3, C4 = 220 nF.

Figure 15. RZREF External Resistor Placement

2.7. Clock Generation

The ProSLIC will generate the necessary internal clock

frequencies from the PCLK input. PCLK must be

synchronous to the 8 kHz FSYNC clock and run at one

of the following rates: 256 kHz, 512 kHz, 768 kHz,

1.024 MHz, 1.536 MHz, 2.048 MHz, 4.096 MHz or

8.192 MHz. The ratio of the PCLK rate to the FSYNC

rate is determined via a counter clocked by PCLK. The

three-bit ratio information is automatically transferred

into an internal register, PLL_MULT, following a reset of

the ProSLIC. The PLL_MULT is used to control the

internal PLL which multiplies PCLK as needed to

generate 16.384 MHz rate needed to run the internal

filters and other circuitry.

The PLL clock synthesizer settles very quickly following

power up. However, the settling time depends on the

The ProSLIC is capable of generating interrupts for the

following events:

Loop current/ring ground detected

Ring trip detected

Power alarm

Active timer 1 expired

Inactive timer 1 expired

Active timer 2 expired

Inactive timer 2 expired

Ringing active timer expired

Ringing inactive timer expired

Indirect register access complete

The interface to the interrupt logic consists of six

registers. Three interrupt status registers contain 1 bit

for each of the above interrupt functions. These bits will

be set when an interrupt is pending for the associated

resource. Three interrupt enable registers also contain 1

bit for each interrupt function. In the case of the interrupt

enable registers, the bits are active high. Refer to the

appropriate functional description section for

operational details of the interrupt functions.

When a resource reaches an interrupt condition, it will

34

Preliminary Rev. 0.5

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