SI4010-C2-GS View Datasheet(PDF) - Silicon Laboratories
Part Name
Description
Manufacturer
SI4010-C2-GS Datasheet PDF : 156 Pages
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Si4010-C2
SFR Definition 30.4. P1CON
Bit
7
6
5
4
3
2
1
0
Name
P1CON[7:0]
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
SFR Address = 0xA5
Bit Name
Function
Port 1 Register GPIO[15:8], Bit Addressable.
This bit controls configuration of each corresponding output bit in P1.
0 .. open-drain, pull up resistor connected (see PORT_ROFF)
7:0 P1CON[7:0] 1 .. push-pull, pull up resistor disabled
If the pin to be input, it must be configured as open-drain and 1 has to be written as
output value to it. Only bits [1:0] corresponding to GPIO[9:8] are used, write to the
rest of the register has no effect, read returns 0 for those bits.
SFR Definition 30.5. P2
Bit
7
6
5
4
3
2
1
0
Name
P2[7:0]
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
SFR Address = 0xA0
Bit Name
Function
Port 2 Register, Bit Addressable.
7:0
P2[7:0]
It is not a port, but a regular register. This register is used as a page MSB address
byte for XDATA addressing in mode, using the PDATA memory accesses. The sole
purpose for it is to support the PDATA model.
120
Rev. 1.0
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