SMB117 View Datasheet(PDF) - Summit Microelectronics

Part Name

Description

Manufacturer

SMB117

High-power, Four-channel Programmable DC-DC System Power Managers

Summit Microelectronics 

SMB113A/B/SMB117/A

Preliminary Information

I2C-2 WIRE SERIAL INTERFACE AC OPERATING CHARACTERISTICS – 100 kHz

(Over recommended operating conditions, unless otherwise noted. All voltages are relative to GND.)

Symbol

Description

Conditions

100kHz

Min Typ Max Units

fSCL

TLOW

THIGH

tBUF

tSU:STA

tHD:STA

tSU:STO

tAA

tDH

tR

tF

tSU:DAT

tHD:DAT

TI

SCL clock frequency

Clock low period

Clock high period

Bus free time

Start condition setup time

Start condition hold time

Stop condition setup time

Clock edge to data valid

Data output hold time

SCL and SDA rise time

SCL and SDA fall time

Data in setup time

Data in hold time

Noise filter SCL and SDA

Before new transmission –

Note 6

SCL low to valid SDA

(cycle n)

SCL low (cycle n+1) to SDA

change

Note 6

Note 6

Noise suppression

0

100 kHz

4.7

μs

4.0

μs

4.7

μs

4.7

μs

4.0

μs

4.7

μs

0.2

3.5 μs

0.2

μs

1000 ns

300 ns

250

ns

0

ns

136

ns

tWR_CONFIG

tWR_EE

Write cycle time config

Write cycle time EE

Configuration registers

Memory array

10 ms

5

ms

Note 6: Guaranteed by Design.

TIMING DIAGRAMS

tR

SCL

tSU:STA

SDA (IN)

SDA (OUT)

tF

tHD:STA

tAA

tHIGH

tHD:DAT

tLOW

tSU:DAT

tDH

tSU:STO

Figure 4 – I2C timing diagram

tWR (For Write Operation Only)

tBUF

Summit Microelectronics, Inc

2111 2.6 9/16/2010

13

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