SP9504JS View Datasheet(PDF) - Signal Processing Technologies
Part Name
Description
Manufacturer
SP9504JS Datasheet PDF : 11 Pages
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SPECIFICATIONS (CONTINUED)
(Typical at 25˚C; TMIN ≤ TA≤TMAX; VDD = +5V, VSS = -5V, VREF = +3V; CMOS logic level digital inputs; specifications apply to all grades unless otherwise noted.)
PARAMETER
MIN. TYP. MAX.
UNITS
CONDITIONS
SWITCHING CHARACTERISTICS
tDS Data Set Up Time
140
100
tDN Data Hold Time
0
tWR Write Pulse Width
140
100
tXFER Transfer Pulse Width
140
100
tWC Total Write Command
280
200
STABILITY
ns
to rising edge of WR1
ns
Figure 4
ns
ns
ns
Gain
15
Bipolar Zero
15
POWER REQUIREMENTS
VDD
–J, –K
VSS
–J, –K
Power Dissipation
8
11
8
11
80
ENVIRONMENTAL AND MECHANICAL
Operating Temperature
–J, –K
Storage
Package
–_P
–_S
0
+70
–60
+150
28–pin Plastic DIP
28–pin SOIC
ppm/˚C
ppm/˚C
mA
mA
mW
°C
°C
t to t
MIN
MAX
tMIN to tMAX
Note 5
+5V, +3%; Note 4, 5
-5V, +3%; Note 4, 5
Notes:
1.
2.
3.
4.
Integral Linearity, for the SP9504, is measured as the arithmetic mean value of the magnitudes of
the greatest positive deviation and the greatest negative deviation from the theoretical value for any
given input condition.
Differential Linearity is the deviation of an output step from the theoretical value of 1 LSB for any two
adjacent digital input codes.
1 LSB = 2*VREF/4,096.
VREF = 0V.
5.
The following power up sequence is recommended to avoid latch up: VSS (-5V), Vdd (+5V), REF IN.
0
DNLE, INLE plots
SP9504DS/03
CODE
Vref = 3V
+0.25 lsb
DNLE
-0.25 lsb
+0.25 lsb
INLE
-0.25 lsb
4095
SP9504 Quad, 12-Bit, Voltage Output D/A Converter
3
© Copyright 2000 Sipex Corporation
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