SSM2118TP View Datasheet(PDF) - Analog Devices
Part Name
Description
Manufacturer
SSM2118TP Datasheet PDF : 16 Pages
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SSM2018T/SSM2118T
V+
COMP 2 COMP 1 VG
–I G
2
8
5
14
3
COMPENSATION
NETWORK
A3
+I 1-G
1
A1
A2
15 BAL
4 –I 1-G
AA44
16 V 1-G
–IN 7
+IN 6
1–G
G
Q1 Q2
G
1–G GAIN
CORE
Q3 Q4
1.8k
Im+(I2s)
200
Im–(I2s) 200
11 V C
13 GND
SPLITTER
VREF
V– 10
Im
9
COMP 3
Figure 38. SSM2018T Detailed Functional Diagram
12 MODE
same is true for the inverting input, which is connected to Pin 1.
The overall feedback ensures that the current flowing through
the input resistors is balanced by the collector currents in Q1
and Q4.
Basic VCA Configuration for the SSM2118T
The SSM2118T behaves very much in the same way as the
SSM2018T except that it has differential current outputs in-
stead of a voltage output. The basic VCA configuration is
shown in Figure 39. A dual output amplifier is needed to re-
place the internal amplifiers in the SSM2018T. However, mul-
tiple SSM2118Ts can share the output amplifiers. The op amps
are configured so that the SSM2118T’s output current is flow-
ing into a virtual ground. This same virtual ground is presented
to all the VCAs, allowing their currents to be summed without
interaction.
OPTIONAL 47k
TRIM
47k
FROM
ADDITIONAL
SSM2118Ts
GLOBAL
SYMMETRY
TRIM
500k
50pF
18k
470k
1
16
V–
2
15
3
14
4 SSM2118T 13
1µF 18k
5
12
VIN+
6
11
VIN–
7
10
1µF 18k
8
9
47pF
V+
50pF*
10k
A2
18k
VOUT
10k
150k
A1
A1, A2: OP275
V–
VCONTROL
3k
1µF 1k
*FOR MORE THAN 2 SSM2118Ts
Figure 39. SSM2118T Typical Bus Summing Application
A global symmetry trim may be necessary, but since it is at the
output amplifiers, only one trim is needed for any number of
SSM2118Ts connected to the summing bus. This trim bal-
ances the resistors around the two amplifiers. If precision,
matched resistors are used, the trim can be removed. However,
to achieve 0.006% distortion, these resistors need to be matched
to approximately 0.01%.
If the choice is made to perform the trim, then one of two meth-
ods may be used. The first method minimizes the distortion of
an audio signal with the SSM2118T in the circuit. To perform
the trim, a 0 dBu, 1 kHz sine wave is applied to one of the
VCAs, and the output distortion is monitored. As the symmetry
trim is adjusted, the output distortion will vary. The optimal
adjustment produces the lowest distortion over the entire trim
range. The second method is to insert a common mode signal
by connecting two 47 kΩ resistors (matched to 0.01%) to the
inverting inputs of each amplifier, as shown in the Figure 39.
The signal is typically a 0 dBu, 1 kHz sine wave, although other
signals can be used. The output is monitored with an oscillo-
scope, and the potentiometer is adjusted to achieve a minimum
output signal.
The SSM2118T has the exact same input and gain core con-
struction as the SSM2018T. Thus, any discussion of these por-
tions of the SSM2018T apply equally to the SSM2118T. The
main difference, which is apparent by comparing Figure 40 to
Figure 38, is the removal of two output amplifiers, A1 and A3.
Instead, the output currents come directly from the collectors of
Q2 and Q3. Notice that the two external amplifiers in Figure
39 are configured the same as the internal amplifiers in the
SSM2018T.
Two important characteristics of these current outputs must be
considered: the output compliance and the effects of capacitive
loading. Normally, the outputs are connected to a virtual
ground node at the summing stage, which is biased at ground.
This bias point can be altered somewhat. The part maintains
good distortion performance for an output compliance from
REV. A
–11–
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