PIC16CR6XT-04/JW View Datasheet(PDF) - Microchip Technology

Part Name

Description

Manufacturer

PIC16CR6XT-04/JW

8-Bit CMOS Microcontrollers

Microchip Technology 

PIC16C6X

FIGURE 4-18: PIR1 REGISTER FOR PIC16C64/64A/R64 (ADDRESS 0Ch)

R/W-0 R/W-0

U-0

PSPIF

—

—

bit7

U-0

R/W-0 R/W-0 R/W-0 R/W-0

—

SSPIF CCP1IF TMR2IF TMR1IF

bit0

bit 7:

bit 6:

bit 5-4:

bit 3:

bit 2:

bit 1:

bit 0:

PSPIF: Parallel Slave Port Interrupt Flag bit

1 = A read or a write operation has taken place (must be cleared in software)

0 = No read or write operation has taken place

Reserved: Always maintain this bit clear.

Unimplemented: Read as '0'

SSPIF: Synchronous Serial Port Interrupt Flag bit

1 = The transmission/reception is complete (must be cleared in software)

0 = Waiting to transmit/receive

CCP1IF: CCP1 Interrupt Flag bit

Capture Mode

1 = A TMR1 register capture occurred (must be cleared in software)

0 = No TMR1 register capture occurred

Compare Mode

1 = A TMR1 register compare match occurred (must be cleared in software)

0 = No TMR1 register compare match occurred

PWM Mode

Unused in this mode

TMR2IF: TMR2 to PR2 Match Interrupt Flag bit

1 = TMR2 to PR2 match occurred (must be cleared in software)

0 = No TMR2 to PR2 match occurred

TMR1IF: TMR1 Overflow Interrupt Flag bit

1 = TMR1 register overflow occurred (must be cleared in software)

0 = No TMR1 register occurred

R = Readable bit

W = Writable bit

U = Unimplemented bit,

read as ‘0’

- n = Value at POR reset

Interrupt flag bits get set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the

global enable bit, GIE (INTCON<7>). User software should ensure the appropriate interrupt flag bits are clear prior to

enabling an interrupt.

© 1997 Microchip Technology Inc.

DS30234D-page 43

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