PIC16C62X
FIGURE 9-17: WATCHDOG TIMER BLOCK DIAGRAM
From TMR0 Clock Source
(Figure 6-6)
Watchdog
Timer
0
M
•
1U
X
WDT
Enable Bit
PSA
Postscaler
8
8 - to -1 MUX
PS<2:0>
•
0
1
MUX
To TMR0 (Figure 6-6)
PSA
WDT
Time-out
Note: T0SE, T0CS, PSA, PS0-PS2 are bits in the OPTION register.
TABLE 9-9: SUMMARY OF WATCHDOG TIMER REGISTERS
Address Name
Bit 7
Bit 6
Bit 5
2007h
Config. bits
---
BOREN CP1
81h
OPTION
RBPU INTEDG T0CS
Legend: Shaded cells are not used by the Watchdog Timer.
Bit 4
CP0
T0SE
Bit 3
PWRTE
PSA
Bit 2
WDTE
PS2
Bit 1
FOSC1
PS1
Bit 0
FOSC0
PS0
Note: _ = Unimplemented location, read as “0”
+ = Reserved for future use
DS30235G-page 58
Preliminary
© 1998 Microchip Technology Inc.