PIC16C7X
Applicable Devices 72 73 73A 74 74A 76 77
FIGURE 20-15: USART SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING
RC6/TX/CK
pin
RC7/RX/DT
pin
121
121
120
122
Note: Refer to Figure 20-1 for load conditions
TABLE 20-11: USART SYNCHRONOUS TRANSMISSION REQUIREMENTS
Param Sym
No.
Characteristic
Min Typ† Max Units Conditions
120 TckH2dtV SYNC XMIT (MASTER &
SLAVE)
Clock high to data out valid
PIC16C76/77
PIC16LC76/77
—
— 80 ns
—
— 100 ns
121 Tckrf
Clock out rise time and fall time PIC16C76/77
(Master Mode)
PIC16LC76/77
—
— 45 ns
—
— 50 ns
122 Tdtrf
Data out rise time and fall time PIC16C76/77
—
— 45 ns
PIC16LC76/77
—
— 50 ns
†: Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
FIGURE 20-16: USART SYNCHRONOUS RECEIVE (MASTER/SLAVE) TIMING
RC6/TX/CK
pin
RC7/RX/DT
pin
125
126
Note: Refer to Figure 20-1 for load conditions
TABLE 20-12: USART SYNCHRONOUS RECEIVE REQUIREMENTS
Parameter Sym
No.
Characteristic
Min
Typ† Max Units Conditions
125
TdtV2ckL SYNC RCV (MASTER & SLAVE)
Data setup before CK ↓ (DT setup time)
15
—
—
ns
126
TckL2dtl Data hold after CK ↓ (DT hold time)
15
—
—
ns
†: Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
© 1997 Microchip Technology Inc.
DS30390E-page 237