PIC16C7X
4.2.2.6
PIE2 REGISTER
Applicable Devices
72 73 73A 74 74A 76 77
This register contains the individual enable bit for the
CCP2 peripheral interrupt.
FIGURE 4-14: PIE2 REGISTER (ADDRESS 8Dh)
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
bit7
bit 7-1: Unimplemented: Read as '0'
bit 0:
CCP2IE: CCP2 Interrupt Enable bit
1 = Enables the CCP2 interrupt
0 = Disables the CCP2 interrupt
U-0
R/W-0
—
CCP2IE R = Readable bit
bit0 W = Writable bit
U = Unimplemented bit,
read as ‘0’
- n = Value at POR reset
© 1997 Microchip Technology Inc.
DS30390E-page 37