ST72334J4B7(2003) View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

ST72334J4B7
(Rev.:2003)

8-BIT MCU WITH SINGLE VOLTAGE FLASH MEMORY, ADC, 16-BIT TIMERS, SPI, SCI INTERFACES

STMicroelectronics 

ST72334J/N, ST72314J/N, ST72124J

16.9 CONTROL PIN CHARACTERISTICS

16.9.1 Asynchronous RESET Pin

Subject to general operating conditions for VDD, fOSC, and TA unless otherwise specified.

Symbol

Parameter

Conditions

Min

Typ 1)

Max

Unit

VIL

VIH

Vhys

VOL

RON

Input low level voltage 2)

Input high level voltage 2)

Schmitt trigger voltage hysteresis 3)

Output low level voltage 4)

(see Figure 92, Figure 93)

Weak pull-up equivalent resistor 5)

tw(RSTL)out Generated reset pulse duration

th(RSTL)in External reset pulse hold time 6)

tg(RSTL)in Filtered glitch duration 7)

0.7xVDD

VDD=5V

IIO=+5mA

IIO=+2mA

VIN=VSS

VDD=5V

VDD=3.4V

20

80

External pin or

internal reset sources

20

400

0.68

0.28

40

100

6

30

0.3xVDD

V

0.95

0.45

60

120

100

mV

V

kΩ

1/fSFOSC

µs

µs

ns

Figure 90. Typical Application with RESET pin 8)

OPTIONAL

USER

EXTERNAL

RESET

CIRCUIT 8)

VDD

VDD

0.1µF 4.7kΩ

0.1µF

VDD

RON

RESET

ST72XXX

INTERNAL

RESET CONTROL

WATCHDOG RESET

LVD RESET

Notes:

1. Unless otherwise specified, typical data are based on TA=25°C and VDD=5V.

2. Data based on characterization results, not tested in production.

3. Hysteresis voltage between Schmitt trigger switching levels. Based on characterization results, not tested.

4. The IIO current sunk must always respect the absolute maximum rating specified in Section 16.2.2 and the sum of IIO

(I/O ports and control pins) must not exceed IVSS.

5. The RON pull-up equivalent resistor is based on a resistive transistor (corresponding ION current characteristics de-

scribed in Figure 91). This data is based on characterization results, not tested in production.

6. To guarantee the reset of the device, a minimum pulse has to be applied to RESET pin. All short pulses applied on

RESET pin with a duration below th(RSTL)in can be ignored.

7. The reset network (the resistor and two capacitors) protects the device against parasitic resets, especially in a noisy

environments.

8. The output of the external reset circuit must have an open-drain output to drive the ST7 reset pad. Otherwise the device

can be damaged when the ST7 generates an internal reset (LVD or watchdog).

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