ST72334J4T1(2003) View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

ST72334J4T1
(Rev.:2003)

8-BIT MCU WITH SINGLE VOLTAGE FLASH MEMORY, ADC, 16-BIT TIMERS, SPI, SCI INTERFACES

STMicroelectronics 

ST72334J/N, ST72314J/N, ST72124J

MAIN CLOCK CONTROLLER WITH REAL TIME CLOCK TIMER (Cont’d)

MISCELLANEOUS REGISTER 1 (MISCR1)

See Section 13 on page 46.

MAIN CLOCK CONTROL/STATUS REGISTER

(MCCSR)

Read /Write

Reset Value: 0000 0001 (01h)

7

0

Bit 0 = OIF Oscillator interrupt flag

This bit is set by hardware and cleared by software

reading the CSR register. It indicates when set

that the main oscillator has measured the selected

elapsed time (TB1:0).

0: Timeout not reached

1: Timeout reached

CAUTION: The BRES and BSET instructions

must not be used on the MCCSR register to avoid

unintentionally clearing the OIF bit.

0

0

0

0 TB1 TB0 OIE OIF

14.2.4 Low Power Modes

Bit 7:4 = Reserved, always read as 0.

Bit 3:2 = TB[1:0] Time base control

These bits select the programmable divider time

base. They are set and cleared by software.

Counter

Prescaler

Time Base

fOSC =8MHz fOSC=16MHz

TB1

TB0

32000

4ms

2ms

0

0

64000

8ms

4ms

0

1

160000

20ms

10ms

1

0

400000

50ms

25ms

1

1

A modification of the time base is taken into ac-

count at the end of the current period (previously

set) to avoid unwanted time shift. This allows to

use this time base as a real time clock.

Bit 1 = OIE Oscillator interrupt enable

This bit set and cleared by software.

0: Oscillator interrupt disabled

1: Oscillator interrupt enabled

This interrupt allows to exit from ACTIVE-HALT

mode.

When this bit is set, calling the ST7 software HALT

instruction enters the ACTIVE-HALT power saving

mode.

Mode

WAIT

ACTIVE-

HALT

HALT

Description

No effect on MCC/RTC peripheral.

MCC/RTC interrupt cause the device to exit

from WAIT mode.

No effect on MCC/RTC counter (OIE bit is

set), the registers are frozen.

MCC/RTC interrupt cause the device to exit

from ACTIVE-HALT mode.

MCC/RTC counter and registers are frozen.

MCC/RTC operation resumes when the

MCU is woken up by an interrupt with “exit

from HALT” capability.

14.2.5 Interrupts

The MCC/RTC interrupt event generates an inter-

rupt if the OIE bit of the MCCSR register is set and

the interrupt mask in the CC register is not active

(RIM instruction).

Interrupt Event

Time base overflow

event

Event

Flag

Enable

Control

Bit

OIF OIE

Exit

from

Wait

Yes

Exit

from

Halt

No 1)

Note:

1. The MCC/RTC interrupt allows to exit from AC-

TIVE-HALT mode, not from HALT mode.

Table 13. MCC Register Map and Reset Values

Address

(Hex.)

Register

Label

7

6

5

0029h

MCCSR

Reset Value

0

0

0

4

3

2

1

0

TB1

TB0

OIE

OIF

0

0

0

0

1

53/153

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