ST72334J/N, ST72314J/N, ST72124J
SERIAL PERIPHERAL INTERFACE (Cont’d)
Figure 45. Data Clock Timing Diagram
SCLK (with
CPOL = 1)
CPHA =1
SCLK (with
CPOL = 0)
MISO
(from master)
MSBit Bit 6 Bit 5 Bit 4 Bit3 Bit 2 Bit 1 LSBit
MOSI
(from slave)
MSBit Bit 6 Bit 5 Bit 4 Bit3 Bit 2 Bit 1 LSBit
SS
(to slave)
CAPTURE STROBE
CPOL = 1
CPHA =0
CPOL = 0
MISO
(from master)
MOSI
(from slave)
MSBit Bit 6
MSBit Bit 6
Bit 5 Bit 4
Bit 5 Bit 4
Bit3 Bit 2 Bit 1 LSBit
Bit3 Bit 2 Bit 1 LSBit
SS
(to slave)
CAPTURE STROBE
Note: This figure should not be used as a replacement for parametric information.
Refer to the Electrical Characteristics chapter.
VR02131B
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