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ST72334J(2003) View Datasheet(PDF) - STMicroelectronics

Part Name
Description
Manufacturer
ST72334J Datasheet PDF : 153 Pages
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ST72334J/N, ST72314J/N, ST72124J
SERIAL COMMUNICATIONS INTERFACE (Cont’d)
EXTENDED RECEIVE PRESCALER DIVISION EXTENDED TRANSMIT PRESCALER DIVISION
REGISTER (ERPR)
REGISTER (ETPR)
Read/Write
Read/Write
Reset Value: 0000 0000 (00 h)
Reset Value:0000 0000 (00h)
Allows setting of the Extended Prescaler rate divi- Allows setting of the External Prescaler rate divi-
sion factor for the receive circuit.
sion factor for the transmit circuit.
7
0
ERPR ERPR ERPR ERPR ERPR ERPR ERPR ERPR
7
6
5
4
3
2
1
0
7
0
ETPR ETPR ETPR ETPR ETPR ETPR ETPR ETPR
7
6
5
4
3
2
1
0
Bit 7:1 = ERPR[7:0] 8-bit Extended Receive Pres-
caler Register.
The extended Baud Rate Generator is activated
when a value different from 00h is stored in this
register. Therefore the clock frequency issued
from the 16 divider (see Figure 3.) is divided by the
binary factor set in the ERPR register (in the range
1 to 255).
The extended baud rate generator is not used af-
ter a reset.
Bit 7:1 = ETPR[7:0] 8-bit Extended Transmit Pres-
caler Register.
The extended Baud Rate Generator is activated
when a value different from 00h is stored in this
register. Therefore the clock frequency issued
from the 16 divider (see Figure 3.) is divided by the
binary factor set in the ETPR register (in the range
1 to 255).
The extended baud rate generator is not used af-
ter a reset.
Table 18. SCI Register Map and Reset Values
Address Register
(Hex.)
Label
0050h
0051h
SCISR
Reset Value
SCIDR
Reset Value
0052h
0053h
0054h
0055h
0057h
SCIBRR
Reset Value
SCICR1
Reset Value
SCICR2
Reset Value
SCIPBRR
Reset Value
SCIPBRT
Reset Value
7
TDRE
1
MSB
x
SOG
0
R8
x
TIE
0
MSB
0
MSB
0
6
TC
1
x
0
T8
x
TCIE
0
0
0
5
4
3
2
1
0
RDRF
0
x
VPOL
x
0
RIE
0
0
0
IDLE
0
x
2FHDET
x
M
x
ILIE
0
0
0
OR
NF
FE
0
0
0
x
x
x
HVSEL VCORDIS CLPINV
x
x
x
WAKE
x
0
0
TE
RE
RWU
0
0
0
0
0
0
0
0
0
0
LSB
x
BLKINV
x
0
SBK
0
LSB
0
LSB
0
96/153

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