ST72314J2B7 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
Manufacturer
ST72314J2B7
STMicroelectronics
ST72314J2B7 Datasheet PDF : 125 Pages
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ST72334J/N, ST72314J/N, ST72124J
MEMORY AND PERIPHERAL CHARACTERISTICS (Cont’d)
SPI Serial Peripheral Interface
Ref. Symbol
Parameter
Cond ition
Value 1)
Min
Max
fSPI SPI frequency
Master
Slave
1/128
1/4
dc
1/2
1
tSPI SPI clock period
Master
Slave
4
2
2
tLead Enable lead time
Slave
120
3
tLag Enable lag time
Slave
120
4
tSPI_H Clock (SCK) high time
Master
Slave
100
90
5
tSPI_L Clock (SCK) low time
Master
Slave
100
90
6
tSU Data set-up time
Master
Slave
100
100
7
tH
Data hold time (inputs)
Master
Slave
100
100
8
tA
Access time (time to data active
from high impedance state)
Slave
9
tDis
Disable time (hold time to high im-
pedance state)
0
120
240
10
tV
Data valid
Master (before capture edge) 0.25
Slave (after enable edge)
120
11
tHold Data hold time (outputs)
Master (before capture edge) 0.25
Slave (after enable edge)
0
12
tRise
Rise time
Outputs: SCK,MOSI,MISO
(20% VDD to 70% VDD, CL = 200pF) Inputs: SCK,MOSI,MISO,SS
100
100
13
tFall
Fall time
Outputs: SCK,MOSI,MISO
(70% VDD to 20% VDD, CL = 200pF) Inputs: SCK,MOSI,MISO,SS
100
100
Unit
fCPU
tCPU
ns
ns
ns
ns
ns
ns
ns
ns
tCPU
ns
tCPU
ns
ns
µs
ns
µs
Figure 59. SPI Master Timing Diagram CPHA=0, CPOL=0 2)
SS
(I NPUT)
1
SCK
(OUTPUT)
MISO
(INPUT)
MOSI
(OUTPUT)
4
D7-IN
6
7
D7-OUT
10
11
5
D6-IN
D6-OUT
13
12
D0-IN
D0-OUT
Notes:
1) Data based on characterization results, not tested in production.
2) Measurement points are VOL, VOH, VIL and VIH in the SPI timing diagram.
VR000109
112/125
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