PIC16LC717T-I/SO View Datasheet(PDF) - Microchip Technology

Part Name

Description

Manufacturer

PIC16LC717T-I/SO

18/20-Pin, 8-Bit CMOS Microcontrollers with 10/12-Bit A/D

Microchip Technology 

PIC16C717/770/771

12.10.1 INT INTERRUPT

External interrupt on RB0/INT pin is edge triggered:

either rising if bit INTEDG (OPTION_REG<6>) is set,

or falling, if the INTEDG bit is clear. When a valid edge

appears on the RB0/INT pin, flag bit INTF

(INTCON<1>) is set. This interrupt can be disabled by

clearing enable bit INTE (INTCON<4>). Flag bit INTF

must be cleared in software in the interrupt service rou-

tine before re-enabling this interrupt. The INT interrupt

can wake-up the processor from SLEEP, if bit INTE was

set prior to going into SLEEP. The status of global inter-

rupt enable bit GIE decides whether or not the proces-

sor branches to the interrupt vector following wake-up.

See Section 12.13 for details on SLEEP mode.

12.10.2 TMR0 INTERRUPT

An overflow (FFh → 00h) in the TMR0 register will set

flag bit T0IF (INTCON<2>). The interrupt can be

enabled/disabled by setting/clearing enable bit T0IE

(INTCON<5>). (Section 2.2.2.3)

12.10.3 PORTB INTCON CHANGE

An input change on PORTB<7:0> sets flag bit RBIF

(INTCON<0>). The PORTB pin(s) which can individu-

ally generate interrupt is selectable in the IOCB regis-

ter. The interrupt can be enabled/disabled by setting/

clearing enable bit RBIE (INTCON<4>).

(Section 2.2.2.3)

12.11 Context Saving During Interrupts

During an interrupt, only the PC is saved on the stack.

At the very least, W and STATUS should be saved to

preserve the context for the interrupted program. All

registers that may be corrupted by the ISR, such as

PCLATH or FSR, should be saved.

Example 12-1 stores and restores the STATUS, W and

PCLATH registers. The register, W_TEMP, is defined in

Common RAM, the last 16 bytes of each bank that may

be accessed from any bank. The STATUS_TEMP and

PCLATH_TEMP are defined in bank 0.

The example:

a) Stores the W register.

b) Stores the STATUS register in bank 0.

c) Stores the PCLATH register in bank 0.

d) Executes the ISR code.

e) Restores the PCLATH register.

f) Restores the STATUS register

g) Restores W.

Note that W_TEMP, STATUS_TEMP and

PCLATH_TEMP are defined in the common RAM area

(70h - 7Fh) to avoid register bank switching during con-

text save and restore.

EXAMPLE 12-1: SAVING STATUS, W, AND PCLATH REGISTERS IN RAM

#define W_TEMP

0x70

#define STATUS_TEMP

0x71

#define PCLATH_TEMP

0x72

org

0x04

; start at Interrupt Vector

MOVWF W_TEMP

; Save W register

MOVF STATUS,w

MOVWF STATUS_TEMP

; save STATUS

MOVF PCLATH,w

MOVWF PCLATH_TEMP

; save PCLATH

:

(Interrupt Service Routine)

:

MOVF PCLATH_TEMP,w

MOVWF PCLATH

MOVF STATUS_TEMP,w

MOVWF STATUS

SWAPF W_TEMP,f

;

SWAPF W_TEMP,w

; swapf loads W without affecting STATUS flags

RETFIE

DS41120A-page 136

Advanced Information

© 1999 Microchip Technology Inc.

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