PIC16C717/770/771
15.5.5 A/D CONVERTER MODULE
TABLE 15-12: PIC16C770/771 AND PIC16LC770/771 A/D CONVERTER CHARACTERISTICS:
Param Sym Characteristic
No.
Min
Typ†
Max Units
Conditions
A01
NR
Resolution
—
—
12 bits bit Min. resolution for A/D is 1 mV,
VREF+ = AVDD = 4.096V,
VREF- = AVSS = 0V,
VREF- ≤ VAIN ≤ VREF+
A03
EIL
Integral error
—
—
TBD
— VREF+ = AVDD = 4.096V,
VREF- = AVSS = 0V,
VREF- ≤ VAIN ≤ VREF+
A04
EDL Differential error
—
—
TBD
— No missing codes to 10 bits
VREF+ = AVDD = 4.096V,
VREF- = AVSS = 0V,
VREF- ≤ VAIN ≤ VREF+
A06
EOFF Offset error
—
—
TBD
— VREF+ = AVDD = 4.096V,
VREF- = AVSS = 0V,
VREF- ≤ VAIN ≤ VREF+
A07
EGN Gain Error
A10
—
Monotonicity
—
—
TBD
LSb VREF+ = AVDD = 4.096V,
VREF- = AVSS = 0V,
VREF- ≤ VAIN ≤ VREF+
—
guaranteed(3)
—
— AVSS ≤ VAIN ≤ VREF+
A20
VREF Reference voltage
4.096
(VREF+ VREF-)
—
VDD +0.3V V Absolute minimum electrical spec to
ensure 12-bit accuracy.
A21
VREF+ Reference V High
VREF-
—
(AVDD or VREF+)
AVDD
V Min. resolution for A/D is 1 mV
A22
VREF- Reference V Low
AVSS
—
VREF+
V Min. resolution for A/D is 1 mV
(AVSS or VREF-)
A25
VAIN Analog input voltage VREFL
—
VREFH
V
A30
ZAIN Recommended
—
—
2.5
kΩ
impedance of analog
voltage source
A50
IREF VREF input current
—
—
10
µA During VAIN acquisition.
(Note 2)
Based on differential of VHOLD to VAIN.
To charge CHOLD see Section 11.0.
During A/D conversion cycle.
* These parameters are characterized but not tested.
† Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
Note 1: When A/D is off, it will not consume any current other than minor leakage current. The power down current spec includes any
such leakage from the A/D module.
2: VREF input current is from External VREF+, or VREF-, or AVSS, or AVDD pin, whichever is selected as reference input.
3: The A/D conversion result never decreases with an increase in the input voltage and has no missing codes.
© 1999 Microchip Technology Inc.
Advanced Information
DS41120A-page 171