PIC16C717TP View Datasheet(PDF) - Microchip Technology

Part Name

Description

Manufacturer

PIC16C717TP

18/20-Pin, 8-Bit CMOS Microcontrollers with 10/12-Bit A/D

Microchip Technology 

PIC16C717/770/771

6.2 Timer1 Oscillator

6.3 Timer1 Interrupt

A crystal oscillator circuit is built in between pins T1OSI

(input) and T1OSO (amplifier output). It is enabled by

setting control bit T1OSCEN (T1CON<3>). The oscilla-

tor is a low power oscillator rated up to 200 kHz. It will

continue to run during SLEEP. It is primarily intended

for a 32 kHz crystal. Table 6-1 shows the capacitor

selection for the Timer1 oscillator.

The Timer1 oscillator is identical to the LP oscillator.

The user must provide a software time delay to ensure

proper oscillator start-up.

TABLE 6-1: CAPACITOR SELECTION FOR

THE TIMER1 OSCILLATOR

The TMR1 Register pair (TMR1H:TMR1L) increments

from 0000h to FFFFh and rolls over to 0000h. The

TMR1 Interrupt, if enabled, is generated on overflow

which is latched in interrupt flag bit TMR1IF (PIR1<0>).

This interrupt can be enabled/disabled by setting/clear-

ing TMR1 interrupt enable bit TMR1IE (PIE1<0>).

6.4 Resetting Timer1 using a CCP Trigger

Output

If the ECCP module is configured in compare mode to

generate a “special event trigger" (CCP1M<3:0> =

1011), this signal will reset Timer1 and start an A/D

conversion (if the A/D module is enabled).

Osc Type

Freq

C1

C2

LP

32 kHz

33 pF

33 pF

100 kHz

15 pF

15 pF

200 kHz

15 pF

15 pF

These values are for design guidance only.

Note 1:

2:

Higher capacitance increases the stability of

oscillator but also increases the start-up time.

Since each resonator/crystal has its own charac-

teristics, the user should consult the resonator/

crystal manufacturer for appropriate values of

external components.

Note:

The special event triggers from the CCP1

module will not set interrupt flag bit

TMR1IF (PIR1<0>).

Timer1 must be configured for either timer or synchro-

nized counter mode to take advantage of this feature. If

Timer1 is running in asynchronous counter mode, this

reset operation may not work.

In the event that a write to Timer1 coincides with a spe-

cial event trigger from ECCP1, the write will take prece-

dence.

In this mode of operation, the CCPR1H:CCPR1L regis-

ters pair effectively becomes the period register for

Timer1.

TABLE 6-2: REGISTERS ASSOCIATED WITH TIMER1 AS A TIMER/COUNTER

Address Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Value on:

POR,

BOR

Value on

all other

resets

0Bh,8Bh,

10Bh,18Bh

0Ch

8Ch

0Eh

0Fh

10h

INTCON

GIE

PEIE

T0IE

INTE

RBIE

T0IF

INTF

RBIF

PIR1

PIE1

TMR1L

TMR1H

T1CON

—

ADIF

—

—

SSPIF

CCP1IF

—

ADIE

—

—

SSPIE

CCP1IE

Holding register for the Least Significant Byte of the 16-bit TMR1 register

Holding register for the Most Significant Byte of the 16-bit TMR1 register

—

— T1CKPS1 T1CKPS0 T1OSCEN T1SYNC

TMR2IF

TMR2IE

TMR1CS

TMR1IF

TMR1IE

TMR1ON

0000 000x

-0-- 0000

-0-- 0000

xxxx xxxx

xxxx xxxx

--00 0000

0000 000u

-0-- 0000

-0-- 0000

uuuu uuuu

uuuu uuuu

--uu uuuu

Legend: x = unknown, u = unchanged, - = unimplemented read as ’0’. Shaded cells are not used by the Timer1 module.

© 1999 Microchip Technology Inc.

Advanced Information

DS41120A-page 51

Share Link: