PIC16C717-I/SS View Datasheet(PDF) - Microchip Technology
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PIC16C717-I/SS Datasheet PDF : 200 Pages
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PIC16C717/770/771
9.2.2 GENERAL CALL ADDRESS SUPPORT
The addressing procedure for the I2C bus is such that
the first byte after the START condition usually deter-
mines which device will be the slave addressed by the
master. The exception is the general call address,
which can address all devices. When this address is
used, all devices should, in theory, respond with an
acknowledge.
The general call address is one of eight addresses
reserved for specific purposes by the I2C protocol. It
consists of all 0’s with R/W = 0
The general call address is recognized when the Gen-
eral Call Enable bit (GCEN) is enabled (SSPCON2<7>
is set). Following a start-bit detect, 8 bits are shifted
into SSPSR and the address is compared against
SSPADD. It is also compared to the general call
address, fixed in hardware.
If the general call address matches, the SSPSR is
transferred to the SSPBUF, the BF flag is set (eighth
bit), and on the falling edge of the ninth bit (ACK bit), the
SSPIF flag is set.
When the interrupt is serviced, the source for the inter-
rupt can be checked by reading the contents of the
SSPBUF to determine if the address was device spe-
cific or a general call address.
In 10-bit mode, the SSPADD is required to be updated
for the second half of the address to match, and the UA
bit is set (SSPSTAT<1>). If the general call address is
sampled when GCEN is set while the slave is config-
ured in 10-bit address mode, then the second half of
the address is not necessary, the UA bit will not be set,
and the slave will begin receiving data after the
acknowledge (Figure 9-13).
FIGURE 9-13: SLAVE MODE GENERAL CALL ADDRESS SEQUENCE (7 OR 10-BIT MODE)
SDA
General Call Address
Address is compared to General Call Address
after ACK, set interrupt flag
R/W = 0
Receiving data
ACK
ACK D7 D6 D5 D4 D3 D2 D1 D0
SCL
SSPIF
S
1 2 34 5 6 78 91 2 34 5 6 78 9
BF
(SSPSTAT<0>)
SSPOV
(SSPCON<6>)
GCEN
(SSPCON2<7>)
Cleared in software
SSPBUF is read
’0’
’1’
© 1999 Microchip Technology Inc.
Advanced Information
DS41120A-page 83
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