ST10R272 View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

ST10R272

16-BIT LOW VOLTAGE ROMLESS MCU WITH MAC

STMicroelectronics 

ST10R272L - MULTIPLY-ACCUMULATE UNIT (MAC)

The following table shows the various combinations of pointer post-modification for each of

these 2 new addressing modes. In this document the symbols “[Rwn⊗]” and “[IDXi⊗]” refer to

these addressing modes.

Symbol

Mnemonic

Address Pointer Operation

“[IDXi⊗]” stands for

[IDXi]

[IDXi+]

(IDXi) ← (IDXi) (no-op)

(IDXi) ← (IDXi) +2 (i=0,1)

[IDXi -]

[IDXi + QXj]

[IDXi - QXj]

(IDXi) ← (IDXi) -2 (i=0,1)

(IDXi) ← (IDXi) + (QXj) (i, j =0,1)

(IDXi) ← (IDXi) - (QXj) (i, j =0,1)

“[Rwn⊗]” stands for

[Rwn]

[Rwn+]

[Rwn-]

[Rwn+QRj]

[Rwn - QRj]

(Rwn) ← (Rwn) (no-op)

(Rwn) ← (Rwn) +2 (n=0-15)

(Rwn) ← (Rwn) -2 (k=0-15)

(Rwn) ← (Rwn) + (QRj) (n=0-15;j =0,1)

(Rwn) ← (Rwn) - (QRj) (n=0-15; j =0,1)

Table 2 Pointer post-modification combinations for IDXi and Rwn

For the CoMACM class of instruction, Parallel Data Move mechanism is implemented. This

class of instruction is only available with double indirect addressing mode. Parallel Data Move

allows the operand pointed by IDXi to be moved to a new location in parallel with the MAC

operation. The write-back address of Parallel Data Move is calculated depending on the post-

modification of IDXi. It is obtained by the reverse operation than the one used to calculate the

new value of IDXi. The following table shows these rules.

Instruction

Writeback Address

CoMACM [IDXi+],...

CoMACM [IDXi-],...

CoMACM [IDXi+QXj],...

CoMACM [IDXi-QXj],...

<IDXi-2>

<IDXi+2>

<IDXi-QXj>

<IDXi+QXj>

Table 3 Parallel data move addressing

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