ST1S10PHR View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

ST1S10PHR

3 A, 900 kHz, monolithic synchronous step-down regulator

STMicroelectronics 

Application information

ST1S10

5.8.4

5.8.5

SCP (short circuit protection)

In order to protect the entire application and reduce the total power dissipation during an

overload or an output short circuit condition, the device is equipped with dynamic short

circuit protection which works by internally monitoring the VFB (feedback voltage).

In the event of an overload or output short circuit, if the VOUT voltage is reduced causing the

feedback voltage (VFB) to drop below 0.3 V (typ.), the device goes into shutdown for the

TOFF time (TOFF(SCP) = 288 µs typ.) and turns on again for the TON period (TON(SCP) = 130

µs typ.). This operation is repeated cycle by cycle, and normal operation is resumed when

no overload is detected (VFB > 0.3 V typ.) for the full TON period.

This dynamic operation can greatly reduce the power dissipation in overload conditions,

while still ensuring excellent power-on startup in most conditions.

SCP and OCP operation with high capacitive load

Thanks to the OCP and SCP circuit, ST1S10 is strongly protected against damage from

short circuit and overload.

However, a highly capacitive load on the output may cause difficulties during start-up. This

can be resolved by using the modified application circuit shown in Figure 3, in which a

minimum of 10 µF for C1 and a 4.7 µF ceramic capacitor for C3 are used. Moreover, for

CLOAD > 100 µF, it is necessary to add the C4 capacitor in parallel to the upper voltage

divider resistor (R1) as shown in Figure 3. The recommended value for C4 is 4.7 nF.

Note that C4 may impact the control loop response and should be added only when a

capacitive load higher than 100 µF is continuously present. If the high capacitive load is

variable or not present at all times, in addition to C4 an increase in the output ceramic

capacitor C2 from 22 µF to 47 µF (or 2 x 22 µF capacitors in parallel) is recommended. Also

in this case it is suggested to further increase the input capacitors to a minimum of 10 µF for

C1 and a 4.7 µF ceramic capacitor for C3 as shown in Figure 3.

Figure 3. Application schematic for heavy capacitive load

12V

VIN_SW

C1

10µF

EN

VIN_A

C3

4.7µF

L1

3.3µH

ST1S10

SW

R1

FB

R2

SYNC

AGND PGND

C4 (*)

4.7nF

5V – 3A

C2(*)

22µF

LOAD

CLOAD

Output Load

(*) see OCP and SCP descriptions for C2 and C4 selection

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