ST20C2 View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

ST20C2

Instruction Set Reference Manual

STMicroelectronics 

shr

shr

shift right

Code: 24 F0

Description: Logical shift right Breg by Areg places, filling with z ero bits. If the initial

Areg is not between 0 and 31 inclusive then the result is zero. The result is only

defined for shift lengths less than the word length.

Definition:

if (0 ≤ Areg < BitsPerWord)

Areg′ ← Breg >> Areg

else

Areg′ ← undefined

Breg′ ← Creg

Creg′ ← undefined

Error signals: none

Comments:

Secondary instruction.

The behavior for shift lengths the outside stated range is implementation

dependent.

See also: lshl lshr norm shl

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