ST25E64 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
Manufacturer
ST25E64 Datasheet PDF : 16 Pages
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Figure 9. Write Modes Sequence with Write Control = 1
ST24E64, ST25E64
WC
BYTE WRITE
ACK
ACK
ACK
NO ACK
DEV SEL
BYTE ADDR BYTE ADDR
DATA IN
R/W
WC
PAGE WRITE
ACK
ACK
ACK
NO ACK
DEV SEL
BYTE ADDR BYTE ADDR DATA IN 1
DATA IN 2
R/W
WC (cont’d)
PAGE WRITE
(cont’d)
NO ACK
NO ACK
DATA IN N
AI01120
sequence. To terminate the stream of bytes, the
master must NOT acknowledge the last byte out-
put, but MUST generate a STOP condition. The
output data is from consecutive byte addresses,
with the internal byte address counter automat-
ically incremented after each byte output. After a
count of the last memory address, the address
counter will ’roll-over’ and the memory will continue
to output data.
Acknowledge in Read Mode. In all read modes
the ST24/25E64 wait for an acknowledge during
the 9th bit time. If the master does not pull the SDA
line low during this time, the ST24/25E64terminate
the data transfer and switch to a standby state.
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