ST486 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
Manufacturer
ST486 Datasheet PDF : 8 Pages
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ST 486 DX ASIC CORE
PAC KA G E O PTIO N S Figure 2. Standard Package Options
PACKAGE
NAME
GQ FP
NUMBER OF LEADS (Pins)
84 100 120 128 144 160 168 176 180 196 208 224 225 256 257 304 313 400 480
PQFP
TQFP
BGA
Plastic
PGA
CPGA
POW
PQFP
with Slug
or
Spreader
: Packages in production
: Packages in development
SIMULATION ENVIRONMENT
The key area of the design flow is the simulation
environment that allows for multiple levels of
design abstraction to be simulated concurrently.
The Cadence Leapfrog/Verilog-XL simulation
engine has been chosen for this “mix and match”
approach, allowing for gate level functional and
timing verification for individual modules to be
Figure 3. Customer Interfaces
performed within a high level description of the
entire device.
CORE MODELS
The ST486DX core can be represented in the
simulation environment through different model
types such as a VHDL bus functional model or a
Model Source hardware model. The Model Source
option utilises ST486DX silicon interfaced to the
VHDL/Verilog software co-simulation environment
through a software shell.
SYSTEM
SYSTEM
BEHAVIO RAL
S P E C IF IC A T IO N
HDL
LEVEL
1
CUSTOMER
RTL HDL
SYNTHESIS
PRE-LAYOUT
GATE LEVEL
SIM U LAT ION
LAYOUT
SGS-THOMSON
PO ST -LAYO U T
GATE LEVEL
SIM U LAT ION
MANUFACT.
AND TEST
LEVEL
2
C U S TO M E R
S G S -T H O M S O N
LEVEL
3
LEVEL
4
C U S TO M E R
C U S TO M E R
SGS-THOMSON
S G S -T H O M S O N
5/8
®
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