ST62P25CB3/CCC View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

ST62P25CB3/CCC

8-BIT MCUs WITH A/D CONVERTER,TWO TIMERS, OSCILLATOR SAFEGUARD & SAFE RESET

STMicroelectronics 

ST6215C/ST6225C

6 INTERRUPTS

The ST6 core may be interrupted by four maska-

ble interrupt sources, in addition to a Non Maska-

ble Interrupt (NMI) source. The interrupt process-

ing flowchart is shown in Figure 18.

Maskable interrupts must be enabled by setting

the GEN bit in the IOR register. However, even if

they are disabled (GEN bit = 0), interrupt events

are latched and may be processed as soon as the

GEN bit is set.

Each source is associated with a specific Interrupt

Vector, located in Program space (see Interrupt

Mapping table). In the vector location, the user

must write a Jump instruction to the associated in-

terrupt service routine.

When an interrupt source generates an interrupt

request, the PC register is loaded with the address

of the interrupt vector, which then causes a Jump

to the relevant interrupt service routine, thus serv-

icing the interrupt.

Interrupts are triggered by events either on exter-

nal pins, or from the on-chip peripherals. Several

events can be ORed on the same interrupt vector.

On-chip peripherals have flag registers to deter-

mine which event triggered the interrupt.

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