ST62T28CM6 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
Manufacturer
ST62T28CM6
STMicroelectronics
ST62T28CM6 Datasheet PDF : 84 Pages
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ST62T28C/E28C
U. A. R. T (Cont’d)
UART Control Register (UARTCR)
Address: D7h, Read/Write
7
0
RXRDY TXMT RXIEN TXIEN BR2 BR1 BR0 PTYEN
Bit 7 = RXRDY. Receiver Ready. This flag be-
comes active as soon as a complete byte has
been received and copied into the receive buffer. It
may be cleared by writing a zero to it. Writing a
one is possible. If the interrupt enable bit RXIEN is
set to one, a software interrupt will be generated.
Bit 6 = TXMT. Transmitter Empty. This flag be-
comes active as soon as a complete byte has
been sent. It may be cleared by writing a zero to it.
It is automatically cleared by the action of writing a
data value into the UART data register.
Bit 5 = RXIEN. Receive Interrupt Enable. When
this bit is set to 1, the receive interrupt is enabled.
Writing to RXIEN does not affect the status of the
interrupt flag RXRDY.
Bit 4 = TXIEN. Transmit Interrupt Enable. When
this bit is set to 1, the transmit interrupt is enabled.
Writing to TXIEN does not affect the status of the
interrupt flag TXRDY.
Bit 3-1= BR2..BR0. Baudrate select. These bits
select the operating baud rate of the UART, de-
pending on the frequency of fOSC. Care should be
taken not to change these bits during communica-
tion as writing to these bits has an immediate ef-
fect.
Bit 0 = PTYEN. Parity/Data Bit 8. The function of
this bit depens on the MCU option set. In 11-bit
frame mode, it is the 9th bit of the trasmitted/re-
ceived character. In 10-bit frame mode, writing a 1
enables the automatic even parity computation,
while a read instruction after reception gives the
parity of the whole 8 bit word received. For the
even parity, a 0 value means no parity error.
Note: As the PTYEN bit is modified in reception, it
must be to set to 1 before transmission if a recep-
tion occured in between.
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