ST62T18CM3 View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

ST62T18CM3

8-BIT MCUs WITH A/D CONVERTER, AUTO-RELOAD TIMER, UART, OSG, SAFE RESET AND 20-PIN PACKAGE

STMicroelectronics 

ST62T18C/E18C

MEMORY MAP (Cont’d)

1.3.3 Data Space

Data Space accommodates all the data necessary

for processing the user program. This space com-

prises the RAM resource, the processor core and

peripheral registers, as well as read-only data

such as constants and look-up tables in Program

memory.

1.3.3.1 Data ROM

All read-only data is physically stored in program

memory, which also accommodates the Program

Space. The program memory consequently con-

tains the program code to be executed, as well as

the constants and look-up tables required by the

application.

The Data Space locations in which the different

constants and look-up tables are addressed by the

processor core may be thought of as a 64-byte

window through which it is possible to access the

read-only data stored in Program memory.

1.3.3.2 Data RAM

In ST62T18C and ST62E18C devices, the data

space includes 60 bytes of RAM, the accumulator

(A), the indirect registers (X), (Y), the short direct

registers (V), (W), the I/O port registers, the pe-

ripheral data and control registers, the interrupt

option register and the Data ROM Window register

(DRW register).

Additional RAM pages can also be addressed us-

ing banks of 64 bytes located between addresses

00h and 3Fh.

1.3.4 Stack Space

Stack space consists of six 12-bit registers which

are used to stack subroutine and interrupt return

addresses, as well as the current program counter

contents.

Table 3. Additional RAM Banks

Device

ST62T18C/E18C

RAM

2 x 64 bytes

Table 4. ST62T18C/E18C Data Memory Space

DATA RAM BANKS

DATA ROM WINDOW AREA

X REGISTER

Y REGISTER

V REGISTER

W REGISTER

DATA RAM

PORT A DATA REGISTER

PORT B DATA REGISTER

RES ERVED

PORT D DATA REGISTE R

PORT A DIRECTION REGISTE R

PORT B DIRECTION REGISTE R

RES ERVED

PORT D DIRECT ION REGISTE R

INTERRUPT OPTION REGISTER

DATA ROM WIND OW REGISTE R

ROM BANK SELECT REGISTE R

RAM BANK SELECT REGISTE R

PORT A OPTION REGISTER

PORT B OPTION REGISTER

RES ERVED

PORT D OPTION REGISTER

A/D DATA REGISTER

A/D CONTROL REGISTER

TIMER 1 PRESCALE R REGISTER

TIMER 1 COUNTE R REGISTER

TIMER 1 STATUS/CONTROL REGISTER

RES ERVED

UART DATA SHIFT REGISTER

UART STATUS CONTROL REGISTER

WATCHDOG REGISTER

RES ERVED

I/O INTER RUPT POLARITY REGISTER

RES ERVED

RES ERVED

RES ERVED

ARTIMER MODE/CONTROL REGISTER

ARTIME R STATUS/CONTROL REGISTER ARSC0

ARTIME R STATUS/CONTROL REGISTER ARSC1

RESE RVED

ARTIMER RELOAD/CAPTURE REGIST ER

ARTIMER COMPARE REGISTER

. ARTIMER LOAD REGISTER

RESE RVED

ACCUMULATOR

* WRIT E ONLY REGISTER

000h

03Fh

040h

07Fh

080h

081h

082h

083h

084h

0BFh

0C0h

0C1h

0C2h

0C3h

0C4h

0C5h

0C6h

0C7h

0C8h*

0C9h*

0CAh*

0CBh*

0CCh

0CDh

0CEh

0CFh

0D0h

0D1h

0D2h

0D3h

0D4h

0D5h

0D6h

0D7h

0D8h

0D9h

0DAh

0DCh*

0DDh

0DEh

0E4h

0E5h

0E6h

0E7h

0E8h

0E9h

0EAh

0EBh

0ECh

OFFh

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