ST62P32BQ6 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
Manufacturer
ST62P32BQ6
STMicroelectronics
ST62P32BQ6 Datasheet PDF : 86 Pages
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ST62T32B ST62E32B
IINTERRUPTS (Cont’d)
Interrupt Polarity Register (IPR)
Address: DAh — Read/Write
7
set, IPR is cleared and all port interrupts are not in-
verted (e.g. Port C generates interrupts on falling
edges).
0
Bit 7 - Bits 5 = Unused.
-
-
- PortE PortD PortC PortA PortB
Bit 4 = Port E Interrupt Polarity.
In conjunction with IOR register ESB bit, the polar-
ity of I/O pins triggered interrupts can be selected
by setting accordingly the Interrupt Polarity Regis-
ter (IPR). If a bit in IPR is set to one the corre-
sponding port interrupt is inverted (e.g. IPR bit 2 =
1 ; port C generates interrupt on rising edge. At re-
Bit 3 = Port D Interrupt Polarity.
Bit 2 = Port C Interrupt Polarity.
Bit 1= Port A Interrupt Polarity.
Bit 0 = Port B Interrupt Polarity.
Table 12. I/O Interrupts selections according to IPR, IOR programming
GEN
1
1
1
1
1
1
1
1
0
IPR3
0
0
0
0
1
1
1
1
X
IPR0
0
0
1
1
0
0
1
1
X
IOR5
0
1
0
1
0
1
0
1
X
Port B occurence
falling edge
rising edge
rising edge
falling edge
falling edge
rising edge
rising edge
falling edge
Disabled
Port D occurence
falling edge
rising edge
falling edge
rising edge
rising edge
falling edge
rising edge
falling edge
Disabled
Int errupt
source
2
GEN
1
1
1
1
1
1
1
1
0
IPR4
0
0
0
0
1
1
1
1
X
IPR1
0
0
1
1
0
0
1
1
X
IOR6
0
1
0
1
0
1
0
1
X
Port A occurence
falling edge
low level
rising edge
high level
falling edge
low level
rising edge
high level
Disabled
Port E occurence
falling edge
low level
falling edge
low level
rising edge
high level
rising edge
high level
Disabled
Int errupt
source
1
IPR2
0
1
Port C occurence
falling edge
rising edge
Interrupt source
0
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