ST62P32BQ6 View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

ST62P32BQ6

8-BIT OTP/EPROM MCUs WITH A/D CONVERTER, 16-BIT AUTO-RELOAD TIMER, EEPROM, SPI AND UART

STMicroelectronics 

ST62T32B ST62E32B

CENTRAL COUNTER (Cont’d)

4.3.1.3 Capture functions

Content of the counter CT can always be down-

loaded (captured) into the CP register at selecta-

ble event occurrence on pins CP1 and CP2, while

capture in RLCP is possible only when the bit

RELOAD is cleared.

Capture functions with RELOAD cleared are used

for period or pulse width measurements with input

CP2, or for phase measurements between two

signals on CP1 and CP2, with the counter in free

running mode. In these modes, counter values by

the two events occurence are stored into RLCP

and CP and the counter remains in free running

mode.

Capture functions with RELOAD set, are used for

same application purpose, but in that case, the

first event reloads the counter from RLCP while

the second event captures the counter content

into the CP register. Therefore, the counter is not

in free running mode for other functions since the

down counting start is initiated by either CP1, CP2

or RUNRES event according to RLDSEL1 and

RLDSEL2 bit.

4.3.2 SIGNAL GENERATION MODES

4.3.2.1 Output modes

Any positive comparison to 0000h or

MASK&CMP, and any overflow occurence can be

used to control the OVF or PWM output pins in

various modes defined by bits OVFMD, PWMPOL,

PWMEN and PWMMD.

PWM pin output modes

MASK & CNT

= 0000h

x

x

no yes no yes

X

MASK&CT=

MASK&CMP

x x yes no yes no

yes

PWMEN

00 1 11 1 1

PWMMD

XX 0 0 0 0 1

PWMPOL

01 0 01 1 X

PWM pin

0 1 Reset Set Set Reset Toggle

OVF pin output modes

Zero overflow (OVFFLG)

OVFMD

OVF pin

1

1

0

1

Set* Toggle

* The OVF pin is reset by clearing the flag OVF-

FLG.

4.3.2.2 Frequency and duty cycles on PWM

pins

In Set/Reset mode (PWMMD=0), the period on the

PWM pin is the time between two matched

masked comparison to 0000h, at which PWM pin

is set (PWMPOL=1) or reset (PWMPOL=0). As

long as no reload function from RLCP is performed

(RELOAD bit cleared) and no mask is used, this

value is 216 x Psc x Tclk. If, on the contrary, reload

function or a mask are used, the frequency is con-

trolled through the RLCP and MASK values (Fig-

ure 29). The condition to reset (PWMPOL=1) or

set back (PWMPOL=0) PWM pin is a matched

masked comparison to CMP. Given a RLCP and

MASK values within the Table 17, CMP defines

the duty cycle.

In Toggle mode (PWMMD=1), PWM pin changes

of state at each positive masked comparison to

CMP value. The frequency is half the frequency in

Set/Reset mode and the duty-cycle is always 50%.

4.3.2.3 Frequency and duty cycles on OVF pin

OVF pin activation is directed by the timer overflow

occurence and therefore its frequency depends

only of the downcounting time from the reload val-

ue to 0000h. This means its period is equal to T=

(RLCP+1) x Psc x Tclk in Set/Reset mode and 2 x

(RLCP+1) x Psc x Tclk in Toggle mode.

Duty cycle is controlled in Set/Reset mode

(OVFMD cleared) by software, since OVF pin can

be reset only by clearing the OVFFLG bit. In toggle

mode (OVFMD set), the duty cycle is always 50%.

Table 18. Achievable periods on PWM pin

Mask value

FF FFh

Period in Set/Reset mode (PWMMD=0) (RLCP+1) x Psc x Tclk

Period in Toggle mode (PWMMD=1) 2 x (RLCP+1) x Psc x Tclk

Note: n is the position of the most significant bit of MASK value.

xxxxh

2 (n+1) x Psc x Tclk

2 x 2 (n+1) x Psc x Tclk

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