ST72P262G1B6/XXX View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

ST72P262G1B6/XXX

8-BIT MCU WITH FLASH OR ROM MEMORY, ADC, TWO 16-BIT TIMERS, I2C, SPI, SCI INTERFACES

STMicroelectronics 

ST72260G, ST72262G, ST72264G

13.9 CONTROL PIN CHARACTERISTICS

13.9.1 Asynchronous RESET Pin

TA = -40 to +85°C unless otherwise specified

Symbol

Parameter

Conditions

Min

Typ

VIL

VIH

Vhys

VOL

Input low level voltage

Input high level voltage

Schmitt trigger voltage hysteresis1)

Output low level voltage 2)

RON Pull-up equivalent resistor

tw(RSTL)out Generated reset pulse duration

th(RSTL)in External reset pulse hold time 4)

tg(RSTL)in Filtered glitch duration 5)

0.85xVDD

VDD=5V

IIO=+5mA

IIO=+2mA

VDD=5V

20

VDD=3V

Internal reset sources

20

2.5

0.68

0.28

40

85

30

200

Figure 99. Typical Application with RESET pin 6)7)8)

Max

0.16xVDD

Unit

V

V

0.95

V

0.45

80

kΩ

µs

µs

ns

Recommended

if LVD is disabled

VDD

VDD

USER

EXTERNAL

RESET

CIRCUIT 5)

0.01µF

4.7kΩ

0.01µF

Required if LVD is disabled

VDD

RON

Filter

PULSE

GENERATOR

ST72XXX

INTERNAL

RESET

WATCHDOG

LVD RESET

Notes:

1. Data based on characterization results, not tested in production.

2. The IIO current sunk must always respect the absolute maximum rating specified in Section 13.2.2 and the sum of IIO

(I/O ports and control pins) must not exceed IVSS.

3. To guarantee the reset of the device, a minimum pulse has to be applied to the RESET pin. All short pulses applied on

RESET pin with a duration below th(RSTL)in can be ignored.

4. The reset network protects the device against parasitic resets.

5. The output of the external reset circuit must have an open-drain output to drive the ST7 reset pad. Otherwise the device

can be damaged when the ST7 generates an internal reset (LVD or watchdog).

6. Whatever the reset source is (internal or external), the user must ensure that the level on the RESET pin can go below

the VIL max. level specified in Section 13.9.1 . Otherwise the reset will not be taken into account internally.

7. Because the reset circuit is designed to allow the internal RESET to be output in the RESET pin, the user must ensure

that the current sunk on the RESET pin (by an external pull-up for example) is less than the absolute maximum value

specified for IINJ(RESET) in Section 13.2.2 on page 123.

147/171

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