ST72260G1B6/XXX View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

ST72260G1B6/XXX

8-BIT MCU WITH FLASH OR ROM MEMORY, ADC, TWO 16-BIT TIMERS, I2C, SPI, SCI INTERFACES

STMicroelectronics 

ST72260G, ST72262G, ST72264G

10 MISCELLANEOUS REGISTERS

The miscellaneous registers allow control over

several different features such as the external in-

terrupts or the I/O alternate functions.

10.1 I/O PORT INTERRUPT SENSITIVITY

The external interrupt sensitivity is controlled by

the ISxx bits of the Miscellaneous register and the

OPTION BYTE. This control allows you to have

two fully independent external interrupt source

sensitivities with configurable sources (using the

EXTIT option bit) as shown in Figure 30 and Fig-

ure 31.

Each external interrupt source can be generated

on four different events on the pin:

s Falling edge

s Rising edge

s Falling and rising edge

s Falling edge and low level

To guarantee correct functionality, the sensitivity

bits in the MISCR1 register must be modified only

when the I[1:0] bits in the CC register are set to 1

(interrupt masked). See Section 9.8 "I/O PORT

REGISTER DESCRIPTION" on page 43 and Sec-

tion 10.3 "MISCELLANEOUS REGISTER DE-

SCRIPTION" on page 46 for more details on the

programming.

10.2 I/O PORT ALTERNATE FUNCTIONS

The MISCR registers manage four I/O port miscel-

laneous alternate functions:

s Main clock signal (fCPU) output on PC2

s SPI pin configuration:

– SS pin internal control to use the PB7 I/O port

function while the SPI is active.

– Master output capability on the MOSI pin

(PB4) deactivated while the SPI is active.

– Slave output capability on the MISO pin (PB5)

deactivated while the SPI is active.

These functions are described in detail in the Sec-

tion 10.3 "MISCELLANEOUS REGISTER DE-

SCRIPTION" on page 46.

Figure 30. Ext. Interrupt Sensitivity (EXTIT=0)

MISCR1

PA7

ei0

IS00 IS01

INTERRUPT

PA0

SOURCE

SENSITIVITY

PC5

CONTROL

PC0

MISCR1

ei1

IS10 IS11

PB7

INTERRUPT

SOURCE

SENSITIVITY

CONTROL

PB0

Figure 31. Ext. Interrupt Sensitivity (EXTIT=1)

MISCR1

ei0

IS00 IS01

PA7

INTERRUPT

SOURCE

SENSITIVITY

CONTROL

PA0

MISCR1

PB7

ei1

IS10 IS11

INTERRUPT

PB0

SOURCE

SENSITIVITY

PC5

CONTROL

PC0

45/171

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