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ST72324J6B1 View Datasheet(PDF) - STMicroelectronics

Part Name
Description
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ST72324J6B1 Datasheet PDF : 161 Pages
First Prev 151 152 153 154 155 156 157 158 159 160
ST72324
15 IMPORTANT NOTES
15.1 Silicon Identification
This document refers to ST72F324/ST72324 de-
vices shown in Table 28 and Table 29. They are
identifiable both by the last letter of the Trace
code marked on the device package and by the
last 3 digits of the Internal Sales Type printed on
the box label.
Table 28. Flash Device Identification
Part
Number
ST72F324
xxxx
ST72F324
xxxx
Trace Code
Internal Sales Type
marked on device on box label
“xxxxxxxxxW”
72F324xxxx$A5
(current revision) 72F324xxxx$U5
“xxxxxxxxxX”
72F324xxxx$A4
72F324xxxx$U4
Table 29. ROM Device Identification
Part
Number
Trace Code
Internal Sales Type
marked on device on box label
ST72324xx
xx
“xxxxxxxxxY”
72324xxxx/xxx$A3
ST72324xx
xx
“xxxxxxxxxA”
72324xxxx/xxx$U1
15.2 ALL FLASH AND ROM DEVICES
15.2.1 External RC option
The External RC clock source option described in
previous datasheet revisions is no longer support-
ed and has been removed from this specification.
15.2.2 CSS Function
The Clock Security System function is not guaran-
teed. The features described in Section 6.4.3 are
subject to revision.
15.2.3 Safe Connection of OSC1/OSC2 Pins
The OSC1 and/or OSC2 pins must not be left un-
connected otherwise the ST7 main oscillator may
start and, in this configuration, could generate an
fOSC clock frequency in excess of the allowed
maximum (>16MHz.), putting the ST7 in an un-
safe/undefined state. Refer to Section 6.2 on page
24.
15.2.4 Unexpected Reset Fetch
If an interrupt request occurs while a "POP CC" in-
struction is executed, the interrupt controller does
not recognise the source of the interrupt and, by
default, passes the RESET vector address to the
CPU.
Workaround
To solve this issue, a "POP CC" instruction must
always be preceded by a "SIM" instruction.
15.2.5 Internal RC Oscillator with LVD
The internal RC can only be used if LVD is ena-
bled.
15.2.6 16-bit Timer PWM Mode
In PWM mode, the first PWM pulse is missed after
writing the value FFFCh in the OC1R register
(OC1HR, OC1LR). It leads to either full or no PWM
during a period, depending on the OLVL1 and
OLVL2 settings.
157/161

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