ST72F324K4B5 View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

ST72F324K4B5

8-BIT MCU WITH NESTED INTERRUPTS, FLASH, 10-BIT ADC, 4 TIMERS, SPI, SCI INTERFACE

STMicroelectronics 

ST72324

16-BIT TIMER (Cont’d)

10.3.4 Low Power Modes

Mode

WAIT

HALT

Description

No effect on 16-bit Timer.

Timer interrupts cause the device to exit from WAIT mode.

16-bit Timer registers are frozen.

In HALT mode, the counter stops counting until Halt mode is exited. Counting resumes from the previous

count when the MCU is woken up by an interrupt with “exit from HALT mode” capability or from the counter

reset value when the MCU is woken up by a RESET.

If an input capture event occurs on the ICAPi pin, the input capture detection circuitry is armed. Consequent-

ly, when the MCU is woken up by an interrupt with “exit from HALT mode” capability, the ICFi bit is set, and

the counter value present when exiting from HALT mode is captured into the ICiR register.

10.3.5 Interrupts

Interrupt Event

Input Capture 1 event/Counter reset in PWM mode

Input Capture 2 event

Output Compare 1 event (not available in PWM mode)

Output Compare 2 event (not available in PWM mode)

Timer Overflow event

Event

Flag

ICF1

ICF2*

OCF1

OCF2*

TOF

Enable

Control

Bit

ICIE

OCIE

TOIE

Exit

from

Wait

Yes

Yes

Yes

Yes

Yes

Exit

from

Halt

No

No

No

No

No

Note: The 16-bit Timer interrupt events are connected to the same interrupt vector (see Interrupts chap-

ter). These events generate an interrupt if the corresponding Enable Control Bit is set and the interrupt

mask in the CC register is reset (RIM instruction).

* The ICF2 and OCF2 bits are forced by hardware to 0 in Timer A, hence there is no interrupt event for

these flags.

10.3.6 Summary of Timer modes

MODES

Input Capture (1 and/or 2)

Output Compare (1 and/or 2)

One Pulse Mode

PWM Mode

Input Capture 1

Yes

Yes

No

No

TIMER RESOURCES

Input Capture 2

Yes2)5)

Yes5)

Output Compare 1 Output Compare 2

Yes

Yes4)

Yes

Yes4)

Not

Recommended1)5)

No

Partially 2)

Not

Recommended3)5)

No

No

1) See note 4 in Section 10.3.3.5 One Pulse Mode

2) See note 5 and 6 in Section 10.3.3.5 One Pulse Mode

3) See note 4 in Section 10.3.3.6 Pulse Width Modulation Mode

4) The TAOC2HR, TAOC2LR registers are write only in Timer A. Output Compare 2 event cannot be gen-

erated, OCF2 is forced by hardware to 0.

5) Input Capture 2 is not implemented in Timer A. ICF2 bit is forced by hardware to 0.

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