ST72324J2BA View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

ST72324J2BA

8-BIT MCU WITH NESTED INTERRUPTS, FLASH, 10-BIT ADC, 4 TIMERS, SPI, SCI INTERFACE

STMicroelectronics 

ST72324

SERIAL COMMUNICATIONS INTERFACE (Cont’d)

10.5.4.7 Parity Control

Parity control (generation of parity bit in trasmis-

sion and and parity chencking in reception) can be

enabled by setting the PCE bit in the SCICR1 reg-

ister. Depending on the frame length defined by

the M bit, the possible SCI frame formats are as

listed in Table 19.

Table 19. Frame Formats

M bit PCE bit

SCI frame

0

0

| SB | 8 bit data | STB |

0

1

| SB | 7-bit data | PB | STB |

1

0

| SB | 9-bit data | STB |

1

1

| SB | 8-bit data PB | STB |

Legend: SB = Start Bit, STB = Stop Bit,

PB = Parity Bit

(PS=0) or an odd number of “1s” if odd parity is se-

lected (PS=1). If the parity check fails, the PE flag

is set in the SCISR register and an interrupt is gen-

erated if PIE is set in the SCICR1 register.

10.5.5 Low Power Modes

Mode

WAIT

Description

No effect on SCI.

SCI interrupts cause the device to exit

from Wait mode.

SCI registers are frozen.

HALT

In Halt mode, the SCI stops transmit-

ting/receiving until Halt mode is exit-

ed.

Note: In case of wake up by an address mark, the

MSB bit of the data is taken into account and not

the parity bit

Even parity: the parity bit is calculated to obtain

an even number of “1s” inside the frame made of

the 7 or 8 LSB bits (depending on whether M is

equal to 0 or 1) and the parity bit.

Ex: data=00110101; 4 bits set => parity bit will be

0 if even parity is selected (PS bit = 0).

Odd parity: the parity bit is calculated to obtain an

odd number of “1s” inside the frame made of the 7

or 8 LSB bits (depending on whether M is equal to

0 or 1) and the parity bit.

Ex: data=00110101; 4 bits set => parity bit will be

1 if odd parity is selected (PS bit = 1).

Transmission mode: If the PCE bit is set then the

MSB bit of the data written in the data register is

not transmitted but is changed by the parity bit.

Reception mode: If the PCE bit is set then the in-

terface checks if the received data byte has an

even number of “1s” if even parity is selected

10.5.6 Interrupts

Interrupt Event

Event

Flag

Enable

Control

Bit

Exit

from

Wait

Transmit Data Register

Empty

TDRE

TIE

Yes

Transmission Com-

plete

TC TCIE Yes

Received Data Ready

to be Read

RDRF

RIE

Yes

Overrun Error Detected OR

Yes

Idle Line Detected

IDLE ILIE Yes

Parity Error

PE PIE Yes

Exit

from

Halt

No

No

No

No

No

No

The SCI interrupt events are connected to the

same interrupt vector.

These events generate an interrupt if the corre-

sponding Enable Control Bit is set and the inter-

rupt mask in the CC register is reset (RIM instruc-

tion).

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