ST72F521R9TC View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

ST72F521R9TC

8-BIT MCU WITH NESTED INTERRUPTS, FLASH, 10-BIT ADC, FIVE TIMERS, SPI, SCI, I2C, CAN INTERFACE

STMicroelectronics 

ST72521

CONTROLLER AREA NETWORK (Cont’d)

10.8.3.4 Bit Timing Logic

The bit timing logic monitors the serial bus-line and

performs sampling and adjustment of the sample

point by synchronizing on the start-bit edge and re-

synchronizing on following edges.

Its operation may be explained simply when the

nominal bit time is divided into three segments as

follows:

– Synchronisation segment (SYNC_SEG): a bit

change is expected to lie within this time seg-

ment. It has a fixed length of one time quanta (1

x tCAN).

– Bit segment 1 (BS1): defines the location of the

sample point. It includes the PROP_SEG and

PHASE_SEG1 of the CAN standard. Its duration

is programmable between 1 and 16 time quanta

but may be automatically lengthened to compen-

sate for positive phase drifts due to differences in

the frequency of the various nodes of the net-

work.

– Bit segment 2 (BS2): defines the location of the

transmit point. It represents the PHASE_SEG2

of the CAN standard. Its duration is programma-

ble between 1 and 8 time quanta but may also be

automatically shortened to compensate for neg-

ative phase drifts.

– Resynchronization Jump Width (RJW): de-

fines an upper bound to the amount of lengthen-

ing or shortening of the bit segments. It is

programmable between 1 and 4 time quanta.

To guarantee the correct behaviour of the CAN

controller, SYNC_SEG + BS1 + BS2 must be

greater than or equal to 5 time quanta.

For a detailed description of the CAN resynchroni-

zation mechanism and other bit timing configura-

tion constraints, please refer to the Bosch CAN

standard 2.0.

As a safeguard against programming errors, the

configuration of the Bit Timing Register (BTR) is

only possible while the device is in STANDBY

mode.

Figure 71. Bit Timing

SYNC_SEG

1 x tCAN

NOMINAL BIT TIME

BIT SEGMENT 1 (BS1)

tBS1

BIT SEGMENT 2 (BS2)

tBS2

SAMPLE POINT

TRANSMIT POINT

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