ST72521AR9TC View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

ST72521AR9TC

8-BIT MCU WITH NESTED INTERRUPTS, FLASH, 10-BIT ADC, FIVE TIMERS, SPI, SCI, I2C, CAN INTERFACE

STMicroelectronics 

ST72521

INTERRUPTS (Cont’d)

Table 7. Interrupt Mapping

N°

Source

Block

Description

RESET Reset

TRAP

Software interrupt

0

TLI

External top level interrupt

1

MCC/RTC Main clock controller time base interrupt

CSS

Safe oscillator activation interrupt

2

ei0

External interrupt port A3..0

3

ei1

External interrupt port F2..0

4

ei2

External interrupt port B3..0

5

ei3

External interrupt port B7..4

6

CAN

CAN peripheral interrupts

7

SPI

SPI peripheral interrupts

8

TIMER A TIMER A peripheral interrupts

9

TIMER B TIMER B peripheral interrupts

10

SCI

SCI Peripheral interrupts

11

AVD

Auxiliary Voltage detector interrupt

12

I2C

I2C Peripheral interrupts

13 PWM ART PWM ART interrupt

Register

Label

Priority

Order

Exit

from

HALT1)

Address

Vector

N/A

EICR

MCCSR

SICSR

Higher

Priority

N/A

CANISR

SPICSR

TASR

TBSR

SCISR

SICSR

Lower

Priority

(see periph)

ARTCSR

yes

no

yes

yes

yes

yes

yes

yes

yes

yes2

no

no

no

no

no

yes3

FFFEh-FFFFh

FFFCh-FFFDh

FFFAh-FFFBh

FFF8h-FFF9h

FFF6h-FFF7h

FFF4h-FFF5h

FFF2h-FFF3h

FFF0h-FFF1h

FFEEh-FFEFh

FFECh-FFEDh

FFEAh-FFEBh

FFE8h-FFE9h

FFE6h-FFE7h

FFE4h-FFE5h

FFE2h-FFE3h

FFE0h-FFE1h

Notes:

1. Valid for HALT mode except for the MCC/RTC or CSS interrupt source which exits from ACTIVE-HALT

mode.

2. Exit from HALT possible when SPI is in slave mode.

3. Exit from HALT possible when PWM ART is in external clock mode.

7.6 EXTERNAL INTERRUPTS

7.6.1 I/O Port Interrupt Sensitivity

The external interrupt sensitivity is controlled by

the IPA, IPB and ISxx bits of the EICR register

(Figure 22). This control allows to have up to 4 fully

independent external interrupt source sensitivities.

Each external interrupt source can be generated

on four (or five) different events on the pin:

s Falling edge

s Rising edge

s Falling and rising edge

s Falling edge and low level

s Rising edge and high level (only for ei0 and ei2)

To guarantee correct functionality, the sensitivity

bits in the EICR register can be modified only

when the I1 and I0 bits of the CC register are both

set to 1 (level 3). This means that interrupts must

be disabled before changing sensitivity.

The pending interrupts are cleared by writing a dif-

ferent value in the ISx[1:0], IPA or IPB bits of the

EICR.

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